xref: /openbmc/u-boot/doc/device-tree-bindings/misc/cros-ec.txt (revision 7b9cb4940575f3b2d368d56ca06d3c0330af4c4b)
1Chrome OS CROS_EC Binding
2======================
3
4The device tree node which describes the operation of the CROS_EC interface
5is as follows:
6
7Required properties :
8- compatible = "google,cros-ec"
9
10Optional properties :
11- spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
12   operation
13- i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
14   operation
15- ec-interrupt : Selects the EC interrupt, defined as a GPIO according
16   to the platform
17- optimise-flash-write : Boolean property - if present then flash blocks
18   containing all 0xff will not be written, since we assume that the EC
19   uses that pattern for erased blocks
20
21The CROS_EC node should appear as a subnode of the interrupt that connects it
22to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
23the unit address on that bus.
24
25
26Example
27=======
28
29	spi@131b0000 {
30		cros-ec@0 {
31			reg = <0>;
32			compatible = "google,cros-ec";
33			spi-max-frequency = <5000000>;
34			ec-interrupt = <&gpio 174 1>;
35			optimise-flash-write;
36			status = "disabled";
37		};
38	};
39