xref: /openbmc/u-boot/doc/device-tree-bindings/gpio/intel,x86-broadwell-pinctrl.txt (revision b24f5c4f27bf6a473fc9a3937a2bbf6ddf0fb104)
1*b24f5c4fSSimon GlassIntel x86 PINCTRL/GPIO controller
2*b24f5c4fSSimon Glass
3*b24f5c4fSSimon GlassPin-muxing on broadwell devices can be described with a node for the PINCTRL
4*b24f5c4fSSimon Glassmaster node and a set of child nodes for each required pin state on the SoC.
5*b24f5c4fSSimon GlassThese pin states use phandles and are referred to but a configuration section
6*b24f5c4fSSimon Glasswhich lists all pins in the device.
7*b24f5c4fSSimon Glass
8*b24f5c4fSSimon GlassThe PINCTRL master node requires the following properties:
9*b24f5c4fSSimon Glass- compatible : "intel,x86-broadwell-pinctrl"
10*b24f5c4fSSimon Glass
11*b24f5c4fSSimon GlassPin state nodes must be sub-nodes of the pinctrl master node. The must have
12*b24f5c4fSSimon Glassa phandle. They can contain the following optional properties:
13*b24f5c4fSSimon Glass- mode-gpio	- forces the pin into GPIO mode
14*b24f5c4fSSimon Glass- output-value	- sets the default output value of the GPIO, 0 (low, default)
15*b24f5c4fSSimon Glass			or 1 (high)
16*b24f5c4fSSimon Glass- direction	- sets the direction of the gpio, either PIN_INPUT (default)
17*b24f5c4fSSimon Glass			or PIN_OUTPUT
18*b24f5c4fSSimon Glass- invert	- the input pin is inverted
19*b24f5c4fSSimon Glass- trigger	- sets the trigger type, either TRIGGER_EDGE (default) or
20*b24f5c4fSSimon Glass			TRIGGER_LEVEL
21*b24f5c4fSSimon Glass- sense-disable - the input state sense is disabled
22*b24f5c4fSSimon Glass- owner		0 sets the owner of the pin, either OWNER_ACPI (default) or
23*b24f5c4fSSimon Glass			ONWER_GPIO
24*b24f5c4fSSimon Glass- route		- sets whether the pin is routed, either PIRQ_APIC_MASK or
25*b24f5c4fSSimon Glass			PIRQ_APIC_ROUTE
26*b24f5c4fSSimon Glass- irq-enable	- the interrupt is enabled
27*b24f5c4fSSimon Glass- reset-rsmrst	- the pin will only be reset by RSMRST
28*b24f5c4fSSimon Glass- pirq-apic	- the pin will be routed to the IOxAPIC
29*b24f5c4fSSimon Glass
30*b24f5c4fSSimon GlassThe first pin state will be the default, so pins without a configuration will
31*b24f5c4fSSimon Glassuse that.
32*b24f5c4fSSimon Glass
33*b24f5c4fSSimon GlassThe pin configuration node is also a sub-node of the pinctrl master node, but
34*b24f5c4fSSimon Glassdoes not have a phandle. It has a single property:
35*b24f5c4fSSimon Glass
36*b24f5c4fSSimon Glass- config	- configuration to use for each pin. Each entry has of 3 cells:
37*b24f5c4fSSimon Glass			- GPIO number (0..94)
38*b24f5c4fSSimon Glass			- phandle of configuration (above)
39*b24f5c4fSSimon Glass			- interrupt number (0..15)
40*b24f5c4fSSimon Glass
41*b24f5c4fSSimon Glass		  There should be one entry for each pin (i.e. 95 entries).
42*b24f5c4fSSimon Glass		  But missing pins will receive the default configuration.
43*b24f5c4fSSimon Glass
44*b24f5c4fSSimon GlassExample:
45*b24f5c4fSSimon Glass
46*b24f5c4fSSimon Glasspch_pinctrl {
47*b24f5c4fSSimon Glass	compatible = "intel,x86-broadwell-pinctrl";
48*b24f5c4fSSimon Glass
49*b24f5c4fSSimon Glass	/* Put this first: it is the default */
50*b24f5c4fSSimon Glass	gpio_unused: gpio-unused {
51*b24f5c4fSSimon Glass		mode-gpio;
52*b24f5c4fSSimon Glass		direction = <PIN_INPUT>;
53*b24f5c4fSSimon Glass		owner = <OWNER_GPIO>;
54*b24f5c4fSSimon Glass		sense-disable;
55*b24f5c4fSSimon Glass	};
56*b24f5c4fSSimon Glass
57*b24f5c4fSSimon Glass	gpio_acpi_sci: acpi-sci {
58*b24f5c4fSSimon Glass		mode-gpio;
59*b24f5c4fSSimon Glass		direction = <PIN_INPUT>;
60*b24f5c4fSSimon Glass		invert;
61*b24f5c4fSSimon Glass		route = <ROUTE_SCI>;
62*b24f5c4fSSimon Glass	};
63*b24f5c4fSSimon Glass
64*b24f5c4fSSimon Glass	gpio_acpi_smi: acpi-smi {
65*b24f5c4fSSimon Glass		mode-gpio;
66*b24f5c4fSSimon Glass		direction = <PIN_INPUT>;
67*b24f5c4fSSimon Glass		invert;
68*b24f5c4fSSimon Glass		route = <ROUTE_SMI>;
69*b24f5c4fSSimon Glass	};
70*b24f5c4fSSimon Glass
71*b24f5c4fSSimon Glass	gpio_input: gpio-input {
72*b24f5c4fSSimon Glass		mode-gpio;
73*b24f5c4fSSimon Glass		direction = <PIN_INPUT>;
74*b24f5c4fSSimon Glass		owner = <OWNER_GPIO>;
75*b24f5c4fSSimon Glass	};
76*b24f5c4fSSimon Glass
77*b24f5c4fSSimon Glass	gpio_input_invert: gpio-input-invert {
78*b24f5c4fSSimon Glass		mode-gpio;
79*b24f5c4fSSimon Glass		direction = <PIN_INPUT>;
80*b24f5c4fSSimon Glass		owner = <OWNER_GPIO>;
81*b24f5c4fSSimon Glass		invert;
82*b24f5c4fSSimon Glass	};
83*b24f5c4fSSimon Glass
84*b24f5c4fSSimon Glass	gpio_native: gpio-native {
85*b24f5c4fSSimon Glass	};
86*b24f5c4fSSimon Glass
87*b24f5c4fSSimon Glass	gpio_out_high: gpio-out-high {
88*b24f5c4fSSimon Glass		mode-gpio;
89*b24f5c4fSSimon Glass		direction = <PIN_OUTPUT>;
90*b24f5c4fSSimon Glass		output-value = <1>;
91*b24f5c4fSSimon Glass		owner = <OWNER_GPIO>;
92*b24f5c4fSSimon Glass		sense-disable;
93*b24f5c4fSSimon Glass	};
94*b24f5c4fSSimon Glass
95*b24f5c4fSSimon Glass	gpio_out_low: gpio-out-low {
96*b24f5c4fSSimon Glass		mode-gpio;
97*b24f5c4fSSimon Glass		direction = <PIN_OUTPUT>;
98*b24f5c4fSSimon Glass		output-value = <0>;
99*b24f5c4fSSimon Glass		owner = <OWNER_GPIO>;
100*b24f5c4fSSimon Glass		sense-disable;
101*b24f5c4fSSimon Glass	};
102*b24f5c4fSSimon Glass
103*b24f5c4fSSimon Glass	gpio_pirq: gpio-pirq {
104*b24f5c4fSSimon Glass		mode-gpio;
105*b24f5c4fSSimon Glass		direction = <PIN_INPUT>;
106*b24f5c4fSSimon Glass		owner = <OWNER_GPIO>;
107*b24f5c4fSSimon Glass		pirq-apic = <PIRQ_APIC_ROUTE>;
108*b24f5c4fSSimon Glass	};
109*b24f5c4fSSimon Glass
110*b24f5c4fSSimon Glass	soc_gpio@0 {
111*b24f5c4fSSimon Glass		config =
112*b24f5c4fSSimon Glass			<0 &gpio_unused 0>,	/* unused */
113*b24f5c4fSSimon Glass			<1 &gpio_unused 0>,	/* unused */
114*b24f5c4fSSimon Glass			<2 &gpio_unused 0>,	/* unused */
115*b24f5c4fSSimon Glass			<3 &gpio_unused 0>,	/* unused */
116*b24f5c4fSSimon Glass			<4 &gpio_native 0>,	/* native: i2c0_sda_gpio4 */
117*b24f5c4fSSimon Glass			<5 &gpio_native 0>,	/* native: i2c0_scl_gpio5 */
118*b24f5c4fSSimon Glass			<6 &gpio_native 0>,	/* native: i2c1_sda_gpio6 */
119*b24f5c4fSSimon Glass			<7 &gpio_native 0>,	/* native: i2c1_scl_gpio7 */
120*b24f5c4fSSimon Glass			<8 &gpio_acpi_sci 0>,	/* pch_lte_wake_l */
121*b24f5c4fSSimon Glass			<9 &gpio_input_invert 0>,/* trackpad_int_l (wake) */
122*b24f5c4fSSimon Glass			<10 &gpio_acpi_sci 0>,	/* pch_wlan_wake_l */
123*b24f5c4fSSimon Glass			<11 &gpio_unused 0>,	/* unused */
124*b24f5c4fSSimon Glass			<12 &gpio_unused 0>,	/* unused */
125*b24f5c4fSSimon Glass			<13 &gpio_pirq 3>,	/* trackpad_int_l (pirql) */
126*b24f5c4fSSimon Glass			<14 &gpio_pirq 4>,	/* touch_int_l (pirqm) */
127*b24f5c4fSSimon Glass			<15 &gpio_unused 0>,	/* unused (strap) */
128*b24f5c4fSSimon Glass			<16 &gpio_input 0>,	/* pch_wp */
129*b24f5c4fSSimon Glass			<17 &gpio_unused 0>,	/* unused */
130*b24f5c4fSSimon Glass			<18 &gpio_unused 0>,	/* unused */
131*b24f5c4fSSimon Glass			<19 &gpio_unused 0>,	/* unused */
132*b24f5c4fSSimon Glass			<20 &gpio_native 0>,	/* pcie_wlan_clkreq_l */
133*b24f5c4fSSimon Glass			<21 &gpio_out_high 0>,	/* pp3300_ssd_en */
134*b24f5c4fSSimon Glass			<22 &gpio_unused 0>,	/* unused */
135*b24f5c4fSSimon Glass			<23 &gpio_out_low 0>,	/* pp3300_autobahn_en */
136*b24f5c4fSSimon Glass			<24 &gpio_unused 0>,	/* unused */
137*b24f5c4fSSimon Glass			<25 &gpio_input 0>,	/* ec_in_rw */
138*b24f5c4fSSimon Glass			<26 &gpio_unused 0>,	/* unused */
139*b24f5c4fSSimon Glass			<27 &gpio_acpi_sci 0>,	/* pch_wake_l */
140*b24f5c4fSSimon Glass			<28 &gpio_unused 0>,	/* unused */
141*b24f5c4fSSimon Glass			<29 &gpio_unused 0>,	/* unused */
142*b24f5c4fSSimon Glass			<30 &gpio_native 0>,	/* native: pch_suswarn_l */
143*b24f5c4fSSimon Glass			<31 &gpio_native 0>,	/* native: acok_buf */
144*b24f5c4fSSimon Glass			<32 &gpio_native 0>,	/* native: lpc_clkrun_l */
145*b24f5c4fSSimon Glass			<33 &gpio_native 0>,	/* native: ssd_devslp */
146*b24f5c4fSSimon Glass			<34 &gpio_acpi_smi 0>,	/* ec_smi_l */
147*b24f5c4fSSimon Glass			<35 &gpio_acpi_smi 0>,	/* pch_nmi_dbg_l (route in nmi_en) */
148*b24f5c4fSSimon Glass			<36 &gpio_acpi_sci 0>,	/* ec_sci_l */
149*b24f5c4fSSimon Glass			<37 &gpio_unused 0>,	/* unused */
150*b24f5c4fSSimon Glass			<38 &gpio_unused 0>,	/* unused */
151*b24f5c4fSSimon Glass			<39 &gpio_unused 0>,	/* unused */
152*b24f5c4fSSimon Glass			<40 &gpio_native 0>,	/* native: pch_usb1_oc_l */
153*b24f5c4fSSimon Glass			<41 &gpio_native 0>,	/* native: pch_usb2_oc_l */
154*b24f5c4fSSimon Glass			<42 &gpio_unused 0>,	/* wlan_disable_l */
155*b24f5c4fSSimon Glass			<43 &gpio_out_high 0>,	/* pp1800_codec_en */
156*b24f5c4fSSimon Glass			<44 &gpio_unused 0>,	/* unused */
157*b24f5c4fSSimon Glass			<45 &gpio_acpi_sci 0>,	/* dsp_int - codec wake */
158*b24f5c4fSSimon Glass			<46 &gpio_pirq 6>,	/* hotword_det_l_3v3 (pirqo) - codec irq */
159*b24f5c4fSSimon Glass			<47 &gpio_out_low 0>,	/* ssd_reset_l */
160*b24f5c4fSSimon Glass			<48 &gpio_unused 0>,	/* unused */
161*b24f5c4fSSimon Glass			<49 &gpio_unused 0>,	/* unused */
162*b24f5c4fSSimon Glass			<50 &gpio_unused 0>,	/* unused */
163*b24f5c4fSSimon Glass			<51 &gpio_unused 0>,	/* unused */
164*b24f5c4fSSimon Glass			<52 &gpio_input 0>,	/* sim_det */
165*b24f5c4fSSimon Glass			<53 &gpio_unused 0>,	/* unused */
166*b24f5c4fSSimon Glass			<54 &gpio_unused 0>,	/* unused */
167*b24f5c4fSSimon Glass			<55 &gpio_unused 0>,	/* unused */
168*b24f5c4fSSimon Glass			<56 &gpio_unused 0>,	/* unused */
169*b24f5c4fSSimon Glass			<57 &gpio_out_high 0>,	/* codec_reset_l */
170*b24f5c4fSSimon Glass			<58 &gpio_unused 0>,	/* unused */
171*b24f5c4fSSimon Glass			<59 &gpio_out_high 0>,	/* lte_disable_l */
172*b24f5c4fSSimon Glass			<60 &gpio_unused 0>,	/* unused */
173*b24f5c4fSSimon Glass			<61 &gpio_native 0>,	/* native: pch_sus_stat */
174*b24f5c4fSSimon Glass			<62 &gpio_native 0>,	/* native: pch_susclk */
175*b24f5c4fSSimon Glass			<63 &gpio_native 0>,	/* native: pch_slp_s5_l */
176*b24f5c4fSSimon Glass			<64 &gpio_unused 0>,	/* unused */
177*b24f5c4fSSimon Glass			<65 &gpio_input 0>,	/* ram_id3 */
178*b24f5c4fSSimon Glass			<66 &gpio_input 0>,	/* ram_id3_old (strap) */
179*b24f5c4fSSimon Glass			<67 &gpio_input 0>,	/* ram_id0 */
180*b24f5c4fSSimon Glass			<68 &gpio_input 0>,	/* ram_id1 */
181*b24f5c4fSSimon Glass			<69 &gpio_input 0>,	/* ram_id2 */
182*b24f5c4fSSimon Glass			<70 &gpio_unused 0>,	/* unused */
183*b24f5c4fSSimon Glass			<71 &gpio_native 0>,	/* native: modphy_en */
184*b24f5c4fSSimon Glass			<72 &gpio_unused 0>,	/* unused */
185*b24f5c4fSSimon Glass			<73 &gpio_unused 0>,	/* unused */
186*b24f5c4fSSimon Glass			<74 &gpio_unused 0>,	/* unused */
187*b24f5c4fSSimon Glass			<75 &gpio_unused 0>,	/* unused */
188*b24f5c4fSSimon Glass			<76 &gpio_unused 0>,	/* unused */
189*b24f5c4fSSimon Glass			<77 &gpio_unused 0>,	/* unused */
190*b24f5c4fSSimon Glass			<78 &gpio_unused 0>,	/* unused */
191*b24f5c4fSSimon Glass			<79 &gpio_unused 0>,	/* unused */
192*b24f5c4fSSimon Glass			<80 &gpio_unused 0>,	/* unused */
193*b24f5c4fSSimon Glass			<81 &gpio_unused 0>,	/* unused */
194*b24f5c4fSSimon Glass			<82 &gpio_native 0>,	/* native: ec_rcin_l */
195*b24f5c4fSSimon Glass			<83 &gpio_native 0>,	/* gspi0_cs */
196*b24f5c4fSSimon Glass			<84 &gpio_native 0>,	/* gspi0_clk */
197*b24f5c4fSSimon Glass			<85 &gpio_native 0>,	/* gspi0_miso */
198*b24f5c4fSSimon Glass			<86 &gpio_native 0>,	/* gspi0_mosi (strap) */
199*b24f5c4fSSimon Glass			<87 &gpio_unused 0>,	/* unused */
200*b24f5c4fSSimon Glass			<88 &gpio_unused 0>,	/* unused */
201*b24f5c4fSSimon Glass			<89 &gpio_out_high 0>,	/* pp3300_sd_en */
202*b24f5c4fSSimon Glass			<90 &gpio_unused 0>,	/* unused */
203*b24f5c4fSSimon Glass			<91 &gpio_unused 0>,	/* unused */
204*b24f5c4fSSimon Glass			<92 &gpio_unused 0>,	/* unused */
205*b24f5c4fSSimon Glass			<93 &gpio_unused 0>,	/* unused */
206*b24f5c4fSSimon Glass			<94 &gpio_unused 0 >;	/* unused */
207*b24f5c4fSSimon Glass	};
208*b24f5c4fSSimon Glass};
209