1*5746b0dfSVignesh R* PCF857x-compatible I/O expanders 2*5746b0dfSVignesh R 3*5746b0dfSVignesh RThe PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be 4*5746b0dfSVignesh Rdriven high by a pull-up current source or driven low to ground. This combines 5*5746b0dfSVignesh Rthe direction and output level into a single bit per line, which can't be read 6*5746b0dfSVignesh Rback. We can't actually know at initialization time whether a line is configured 7*5746b0dfSVignesh R(a) as output and driving the signal low/high, or (b) as input and reporting a 8*5746b0dfSVignesh Rlow/high value, without knowing the last value written since the chip came out 9*5746b0dfSVignesh Rof reset (if any). The only reliable solution for setting up line direction is 10*5746b0dfSVignesh Rthus to do it explicitly. 11*5746b0dfSVignesh R 12*5746b0dfSVignesh RRequired Properties: 13*5746b0dfSVignesh R 14*5746b0dfSVignesh R - compatible: should be one of the following. 15*5746b0dfSVignesh R - "maxim,max7328": For the Maxim MAX7378 16*5746b0dfSVignesh R - "maxim,max7329": For the Maxim MAX7329 17*5746b0dfSVignesh R - "nxp,pca8574": For the NXP PCA8574 18*5746b0dfSVignesh R - "nxp,pca8575": For the NXP PCA8575 19*5746b0dfSVignesh R - "nxp,pca9670": For the NXP PCA9670 20*5746b0dfSVignesh R - "nxp,pca9671": For the NXP PCA9671 21*5746b0dfSVignesh R - "nxp,pca9672": For the NXP PCA9672 22*5746b0dfSVignesh R - "nxp,pca9673": For the NXP PCA9673 23*5746b0dfSVignesh R - "nxp,pca9674": For the NXP PCA9674 24*5746b0dfSVignesh R - "nxp,pca9675": For the NXP PCA9675 25*5746b0dfSVignesh R - "nxp,pcf8574": For the NXP PCF8574 26*5746b0dfSVignesh R - "nxp,pcf8574a": For the NXP PCF8574A 27*5746b0dfSVignesh R - "nxp,pcf8575": For the NXP PCF8575 28*5746b0dfSVignesh R - "ti,tca9554": For the TI TCA9554 29*5746b0dfSVignesh R 30*5746b0dfSVignesh R - reg: I2C slave address. 31*5746b0dfSVignesh R 32*5746b0dfSVignesh R - gpio-controller: Marks the device node as a gpio controller. 33*5746b0dfSVignesh R - #gpio-cells: Should be 2. The first cell is the GPIO number and the second 34*5746b0dfSVignesh R cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the 35*5746b0dfSVignesh R GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. 36*5746b0dfSVignesh R 37*5746b0dfSVignesh ROptional Properties: 38*5746b0dfSVignesh R 39*5746b0dfSVignesh R - lines-initial-states: Bitmask that specifies the initial state of each 40*5746b0dfSVignesh R line. When a bit is set to zero, the corresponding line will be initialized to 41*5746b0dfSVignesh R the input (pulled-up) state. When the bit is set to one, the line will be 42*5746b0dfSVignesh R initialized the low-level output state. If the property is not specified 43*5746b0dfSVignesh R all lines will be initialized to the input state. 44*5746b0dfSVignesh R 45*5746b0dfSVignesh R The I/O expander can detect input state changes, and thus optionally act as 46*5746b0dfSVignesh R an interrupt controller. When the expander interrupt line is connected all the 47*5746b0dfSVignesh R following properties must be set. For more information please see the 48*5746b0dfSVignesh R interrupt controller device tree bindings documentation available at 49*5746b0dfSVignesh R Documentation/devicetree/bindings/interrupt-controller/interrupts.txt. 50*5746b0dfSVignesh R 51*5746b0dfSVignesh R - interrupt-controller: Identifies the node as an interrupt controller. 52*5746b0dfSVignesh R - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2. 53*5746b0dfSVignesh R - interrupt-parent: phandle of the parent interrupt controller. 54*5746b0dfSVignesh R - interrupts: Interrupt specifier for the controllers interrupt. 55*5746b0dfSVignesh R 56*5746b0dfSVignesh R 57*5746b0dfSVignesh RPlease refer to gpio.txt in this directory for details of the common GPIO 58*5746b0dfSVignesh Rbindings used by client devices. 59*5746b0dfSVignesh R 60*5746b0dfSVignesh RExample: PCF8575 I/O expander node 61*5746b0dfSVignesh R 62*5746b0dfSVignesh R pcf8575: gpio@20 { 63*5746b0dfSVignesh R compatible = "nxp,pcf8575"; 64*5746b0dfSVignesh R reg = <0x20>; 65*5746b0dfSVignesh R interrupt-parent = <&irqpin2>; 66*5746b0dfSVignesh R interrupts = <3 0>; 67*5746b0dfSVignesh R gpio-controller; 68*5746b0dfSVignesh R #gpio-cells = <2>; 69*5746b0dfSVignesh R interrupt-controller; 70*5746b0dfSVignesh R #interrupt-cells = <2>; 71*5746b0dfSVignesh R }; 72