1NVIDIA Tegra Boot and Power Management Processor (BPMP) 2 3The BPMP is a specific processor in Tegra chip, which is designed for 4booting process handling and offloading the power management, clock 5management, and reset control tasks from the CPU. The binding document 6defines the resources that would be used by the BPMP firmware driver, 7which can create the interprocessor communication (IPC) between the CPU 8and BPMP. 9 10Required properties: 11- name : Should be bpmp 12- compatible 13 Array of strings 14 One of: 15 - "nvidia,tegra186-bpmp" 16- mboxes : The phandle of mailbox controller and the mailbox specifier. 17- shmem : List of the phandle of the TX and RX shared memory area that 18 the IPC between CPU and BPMP is based on. 19- #clock-cells : Should be 1. 20- #power-domain-cells : Should be 1. 21- #reset-cells : Should be 1. 22 23This node is a mailbox consumer. See the following files for details of 24the mailbox subsystem, and the specifiers implemented by the relevant 25provider(s): 26 27- .../mailbox/mailbox.txt 28- .../mailbox/nvidia,tegra186-hsp.txt 29 30This node is a clock, power domain, and reset provider. See the following 31files for general documentation of those features, and the specifiers 32implemented by this node: 33 34- .../clock/clock-bindings.txt 35- <dt-bindings/clock/tegra186-clock.h> 36- ../power/power_domain.txt 37- <dt-bindings/power/tegra186-powergate.h> 38- .../reset/reset.txt 39- <dt-bindings/reset/tegra186-reset.h> 40 41The shared memory bindings for BPMP 42----------------------------------- 43 44The shared memory area for the IPC TX and RX between CPU and BPMP are 45predefined and work on top of sysram, which is an SRAM inside the chip. 46 47See ".../sram/sram.txt" for the bindings. 48 49Example: 50 51hsp_top0: hsp@03c00000 { 52 ... 53 #mbox-cells = <2>; 54}; 55 56sysram@30000000 { 57 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 58 reg = <0x0 0x30000000 0x0 0x50000>; 59 #address-cells = <2>; 60 #size-cells = <2>; 61 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 62 63 cpu_bpmp_tx: bpmp_shmem@4e000 { 64 compatible = "nvidia,tegra186-bpmp-shmem"; 65 reg = <0x0 0x4e000 0x0 0x1000>; 66 }; 67 68 cpu_bpmp_rx: bpmp_shmem@4f000 { 69 compatible = "nvidia,tegra186-bpmp-shmem"; 70 reg = <0x0 0x4f000 0x0 0x1000>; 71 }; 72}; 73 74bpmp { 75 compatible = "nvidia,tegra186-bpmp"; 76 mboxes = <&hsp_top0 HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; 77 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 78 #clock-cells = <1>; 79 #power-domain-cells = <1>; 80 #reset-cells = <1>; 81}; 82