1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2002-2006 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * 6 * (C) Copyright 2002 7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 8 * Marius Groeger <mgroeger@sysgo.de> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <common.h> 14 #include <console.h> 15 #include <environment.h> 16 #include <dm.h> 17 #include <fdtdec.h> 18 #include <fs.h> 19 #include <i2c.h> 20 #include <initcall.h> 21 #include <init_helpers.h> 22 #include <logbuff.h> 23 #include <malloc.h> 24 #include <mapmem.h> 25 26 /* TODO: Can we move these into arch/ headers? */ 27 #ifdef CONFIG_8xx 28 #include <mpc8xx.h> 29 #endif 30 #ifdef CONFIG_5xx 31 #include <mpc5xx.h> 32 #endif 33 #ifdef CONFIG_MPC5xxx 34 #include <mpc5xxx.h> 35 #endif 36 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 37 #include <asm/mp.h> 38 #endif 39 40 #include <os.h> 41 #include <post.h> 42 #include <relocate.h> 43 #include <spi.h> 44 #include <status_led.h> 45 #include <timer.h> 46 #include <trace.h> 47 #include <video.h> 48 #include <watchdog.h> 49 #include <asm/io.h> 50 #include <asm/sections.h> 51 #include <dm/root.h> 52 #include <linux/errno.h> 53 54 /* 55 * Pointer to initial global data area 56 * 57 * Here we initialize it if needed. 58 */ 59 #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR 60 #undef XTRN_DECLARE_GLOBAL_DATA_PTR 61 #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ 62 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); 63 #else 64 DECLARE_GLOBAL_DATA_PTR; 65 #endif 66 67 /* 68 * TODO(sjg@chromium.org): IMO this code should be 69 * refactored to a single function, something like: 70 * 71 * void led_set_state(enum led_colour_t colour, int on); 72 */ 73 /************************************************************************ 74 * Coloured LED functionality 75 ************************************************************************ 76 * May be supplied by boards if desired 77 */ 78 __weak void coloured_LED_init(void) {} 79 __weak void red_led_on(void) {} 80 __weak void red_led_off(void) {} 81 __weak void green_led_on(void) {} 82 __weak void green_led_off(void) {} 83 __weak void yellow_led_on(void) {} 84 __weak void yellow_led_off(void) {} 85 __weak void blue_led_on(void) {} 86 __weak void blue_led_off(void) {} 87 88 /* 89 * Why is gd allocated a register? Prior to reloc it might be better to 90 * just pass it around to each function in this file? 91 * 92 * After reloc one could argue that it is hardly used and doesn't need 93 * to be in a register. Or if it is it should perhaps hold pointers to all 94 * global data for all modules, so that post-reloc we can avoid the massive 95 * literal pool we get on ARM. Or perhaps just encourage each module to use 96 * a structure... 97 */ 98 99 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG) 100 static int init_func_watchdog_init(void) 101 { 102 # if defined(CONFIG_HW_WATCHDOG) && \ 103 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \ 104 defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \ 105 defined(CONFIG_DESIGNWARE_WATCHDOG) || \ 106 defined(CONFIG_IMX_WATCHDOG)) 107 hw_watchdog_init(); 108 puts(" Watchdog enabled\n"); 109 # endif 110 WATCHDOG_RESET(); 111 112 return 0; 113 } 114 115 int init_func_watchdog_reset(void) 116 { 117 WATCHDOG_RESET(); 118 119 return 0; 120 } 121 #endif /* CONFIG_WATCHDOG */ 122 123 __weak void board_add_ram_info(int use_default) 124 { 125 /* please define platform specific board_add_ram_info() */ 126 } 127 128 static int init_baud_rate(void) 129 { 130 gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); 131 return 0; 132 } 133 134 static int display_text_info(void) 135 { 136 #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP) 137 ulong bss_start, bss_end, text_base; 138 139 bss_start = (ulong)&__bss_start; 140 bss_end = (ulong)&__bss_end; 141 142 #ifdef CONFIG_SYS_TEXT_BASE 143 text_base = CONFIG_SYS_TEXT_BASE; 144 #else 145 text_base = CONFIG_SYS_MONITOR_BASE; 146 #endif 147 148 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", 149 text_base, bss_start, bss_end); 150 #endif 151 152 #ifdef CONFIG_USE_IRQ 153 debug("IRQ Stack: %08lx\n", IRQ_STACK_START); 154 debug("FIQ Stack: %08lx\n", FIQ_STACK_START); 155 #endif 156 157 return 0; 158 } 159 160 static int announce_dram_init(void) 161 { 162 puts("DRAM: "); 163 return 0; 164 } 165 166 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) 167 static int init_func_ram(void) 168 { 169 return initdram(); 170 } 171 #endif 172 173 static int show_dram_config(void) 174 { 175 unsigned long long size; 176 177 #ifdef CONFIG_NR_DRAM_BANKS 178 int i; 179 180 debug("\nRAM Configuration:\n"); 181 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 182 size += gd->bd->bi_dram[i].size; 183 debug("Bank #%d: %llx ", i, 184 (unsigned long long)(gd->bd->bi_dram[i].start)); 185 #ifdef DEBUG 186 print_size(gd->bd->bi_dram[i].size, "\n"); 187 #endif 188 } 189 debug("\nDRAM: "); 190 #else 191 size = gd->ram_size; 192 #endif 193 194 print_size(size, ""); 195 board_add_ram_info(0); 196 putc('\n'); 197 198 return 0; 199 } 200 201 __weak int dram_init_banksize(void) 202 { 203 #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) 204 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 205 gd->bd->bi_dram[0].size = get_effective_memsize(); 206 #endif 207 208 return 0; 209 } 210 211 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) 212 static int init_func_i2c(void) 213 { 214 puts("I2C: "); 215 #ifdef CONFIG_SYS_I2C 216 i2c_init_all(); 217 #else 218 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 219 #endif 220 puts("ready\n"); 221 return 0; 222 } 223 #endif 224 225 #if defined(CONFIG_HARD_SPI) 226 static int init_func_spi(void) 227 { 228 puts("SPI: "); 229 spi_init(); 230 puts("ready\n"); 231 return 0; 232 } 233 #endif 234 235 __maybe_unused 236 static int zero_global_data(void) 237 { 238 memset((void *)gd, '\0', sizeof(gd_t)); 239 240 return 0; 241 } 242 243 static int setup_mon_len(void) 244 { 245 #if defined(__ARM__) || defined(__MICROBLAZE__) 246 gd->mon_len = (ulong)&__bss_end - (ulong)_start; 247 #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP) 248 gd->mon_len = (ulong)&_end - (ulong)_init; 249 #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA) 250 gd->mon_len = CONFIG_SYS_MONITOR_LEN; 251 #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) 252 gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start); 253 #elif defined(CONFIG_SYS_MONITOR_BASE) 254 /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ 255 gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; 256 #endif 257 return 0; 258 } 259 260 __weak int arch_cpu_init(void) 261 { 262 return 0; 263 } 264 265 __weak int mach_cpu_init(void) 266 { 267 return 0; 268 } 269 270 /* Get the top of usable RAM */ 271 __weak ulong board_get_usable_ram_top(ulong total_size) 272 { 273 #ifdef CONFIG_SYS_SDRAM_BASE 274 /* 275 * Detect whether we have so much RAM that it goes past the end of our 276 * 32-bit address space. If so, clip the usable RAM so it doesn't. 277 */ 278 if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) 279 /* 280 * Will wrap back to top of 32-bit space when reservations 281 * are made. 282 */ 283 return 0; 284 #endif 285 return gd->ram_top; 286 } 287 288 static int setup_dest_addr(void) 289 { 290 debug("Monitor len: %08lX\n", gd->mon_len); 291 /* 292 * Ram is setup, size stored in gd !! 293 */ 294 debug("Ram size: %08lX\n", (ulong)gd->ram_size); 295 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 296 /* 297 * Subtract specified amount of memory to hide so that it won't 298 * get "touched" at all by U-Boot. By fixing up gd->ram_size 299 * the Linux kernel should now get passed the now "corrected" 300 * memory size and won't touch it either. This should work 301 * for arch/ppc and arch/powerpc. Only Linux board ports in 302 * arch/powerpc with bootwrapper support, that recalculate the 303 * memory size from the SDRAM controller setup will have to 304 * get fixed. 305 */ 306 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; 307 #endif 308 #ifdef CONFIG_SYS_SDRAM_BASE 309 gd->ram_top = CONFIG_SYS_SDRAM_BASE; 310 #endif 311 gd->ram_top += get_effective_memsize(); 312 gd->ram_top = board_get_usable_ram_top(gd->mon_len); 313 gd->relocaddr = gd->ram_top; 314 debug("Ram top: %08lX\n", (ulong)gd->ram_top); 315 #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) 316 /* 317 * We need to make sure the location we intend to put secondary core 318 * boot code is reserved and not used by any part of u-boot 319 */ 320 if (gd->relocaddr > determine_mp_bootpg(NULL)) { 321 gd->relocaddr = determine_mp_bootpg(NULL); 322 debug("Reserving MP boot page to %08lx\n", gd->relocaddr); 323 } 324 #endif 325 return 0; 326 } 327 328 #if defined(CONFIG_LOGBUFFER) 329 static int reserve_logbuffer(void) 330 { 331 #ifndef CONFIG_ALT_LB_ADDR 332 /* reserve kernel log buffer */ 333 gd->relocaddr -= LOGBUFF_RESERVE; 334 debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, 335 gd->relocaddr); 336 #endif 337 338 return 0; 339 } 340 #endif 341 342 #ifdef CONFIG_PRAM 343 /* reserve protected RAM */ 344 static int reserve_pram(void) 345 { 346 ulong reg; 347 348 reg = getenv_ulong("pram", 10, CONFIG_PRAM); 349 gd->relocaddr -= (reg << 10); /* size is in kB */ 350 debug("Reserving %ldk for protected RAM at %08lx\n", reg, 351 gd->relocaddr); 352 return 0; 353 } 354 #endif /* CONFIG_PRAM */ 355 356 /* Round memory pointer down to next 4 kB limit */ 357 static int reserve_round_4k(void) 358 { 359 gd->relocaddr &= ~(4096 - 1); 360 return 0; 361 } 362 363 #ifdef CONFIG_ARM 364 static int reserve_mmu(void) 365 { 366 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) 367 /* reserve TLB table */ 368 gd->arch.tlb_size = PGTABLE_SIZE; 369 gd->relocaddr -= gd->arch.tlb_size; 370 371 /* round down to next 64 kB limit */ 372 gd->relocaddr &= ~(0x10000 - 1); 373 374 gd->arch.tlb_addr = gd->relocaddr; 375 debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, 376 gd->arch.tlb_addr + gd->arch.tlb_size); 377 378 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE 379 /* 380 * Record allocated tlb_addr in case gd->tlb_addr to be overwritten 381 * with location within secure ram. 382 */ 383 gd->arch.tlb_allocated = gd->arch.tlb_addr; 384 #endif 385 #endif 386 387 return 0; 388 } 389 #endif 390 391 static int reserve_video(void) 392 { 393 #ifdef CONFIG_DM_VIDEO 394 ulong addr; 395 int ret; 396 397 addr = gd->relocaddr; 398 ret = video_reserve(&addr); 399 if (ret) 400 return ret; 401 gd->relocaddr = addr; 402 #elif defined(CONFIG_LCD) 403 # ifdef CONFIG_FB_ADDR 404 gd->fb_base = CONFIG_FB_ADDR; 405 # else 406 /* reserve memory for LCD display (always full pages) */ 407 gd->relocaddr = lcd_setmem(gd->relocaddr); 408 gd->fb_base = gd->relocaddr; 409 # endif /* CONFIG_FB_ADDR */ 410 #elif defined(CONFIG_VIDEO) && \ 411 (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) && \ 412 !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \ 413 !defined(CONFIG_M68K) 414 /* reserve memory for video display (always full pages) */ 415 gd->relocaddr = video_setmem(gd->relocaddr); 416 gd->fb_base = gd->relocaddr; 417 #endif 418 419 return 0; 420 } 421 422 static int reserve_trace(void) 423 { 424 #ifdef CONFIG_TRACE 425 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE; 426 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE); 427 debug("Reserving %dk for trace data at: %08lx\n", 428 CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr); 429 #endif 430 431 return 0; 432 } 433 434 static int reserve_uboot(void) 435 { 436 /* 437 * reserve memory for U-Boot code, data & bss 438 * round down to next 4 kB limit 439 */ 440 gd->relocaddr -= gd->mon_len; 441 gd->relocaddr &= ~(4096 - 1); 442 #ifdef CONFIG_E500 443 /* round down to next 64 kB limit so that IVPR stays aligned */ 444 gd->relocaddr &= ~(65536 - 1); 445 #endif 446 447 debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, 448 gd->relocaddr); 449 450 gd->start_addr_sp = gd->relocaddr; 451 452 return 0; 453 } 454 455 /* reserve memory for malloc() area */ 456 static int reserve_malloc(void) 457 { 458 gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN; 459 debug("Reserving %dk for malloc() at: %08lx\n", 460 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp); 461 return 0; 462 } 463 464 /* (permanently) allocate a Board Info struct */ 465 static int reserve_board(void) 466 { 467 if (!gd->bd) { 468 gd->start_addr_sp -= sizeof(bd_t); 469 gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t)); 470 memset(gd->bd, '\0', sizeof(bd_t)); 471 debug("Reserving %zu Bytes for Board Info at: %08lx\n", 472 sizeof(bd_t), gd->start_addr_sp); 473 } 474 return 0; 475 } 476 477 static int setup_machine(void) 478 { 479 #ifdef CONFIG_MACH_TYPE 480 gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ 481 #endif 482 return 0; 483 } 484 485 static int reserve_global_data(void) 486 { 487 gd->start_addr_sp -= sizeof(gd_t); 488 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t)); 489 debug("Reserving %zu Bytes for Global Data at: %08lx\n", 490 sizeof(gd_t), gd->start_addr_sp); 491 return 0; 492 } 493 494 static int reserve_fdt(void) 495 { 496 #ifndef CONFIG_OF_EMBED 497 /* 498 * If the device tree is sitting immediately above our image then we 499 * must relocate it. If it is embedded in the data section, then it 500 * will be relocated with other data. 501 */ 502 if (gd->fdt_blob) { 503 gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); 504 505 gd->start_addr_sp -= gd->fdt_size; 506 gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size); 507 debug("Reserving %lu Bytes for FDT at: %08lx\n", 508 gd->fdt_size, gd->start_addr_sp); 509 } 510 #endif 511 512 return 0; 513 } 514 515 int arch_reserve_stacks(void) 516 { 517 return 0; 518 } 519 520 static int reserve_stacks(void) 521 { 522 /* make stack pointer 16-byte aligned */ 523 gd->start_addr_sp -= 16; 524 gd->start_addr_sp &= ~0xf; 525 526 /* 527 * let the architecture-specific code tailor gd->start_addr_sp and 528 * gd->irq_sp 529 */ 530 return arch_reserve_stacks(); 531 } 532 533 static int display_new_sp(void) 534 { 535 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp); 536 537 return 0; 538 } 539 540 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 541 defined(CONFIG_SH) 542 static int setup_board_part1(void) 543 { 544 bd_t *bd = gd->bd; 545 546 /* 547 * Save local variables to board info struct 548 */ 549 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ 550 bd->bi_memsize = gd->ram_size; /* size in bytes */ 551 552 #ifdef CONFIG_SYS_SRAM_BASE 553 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ 554 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ 555 #endif 556 557 #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) || defined(CONFIG_5xx) || \ 558 defined(CONFIG_E500) || defined(CONFIG_MPC86xx) 559 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ 560 #endif 561 #if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K) 562 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ 563 #endif 564 #if defined(CONFIG_MPC83xx) 565 bd->bi_immrbar = CONFIG_SYS_IMMR; 566 #endif 567 568 return 0; 569 } 570 #endif 571 572 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 573 static int setup_board_part2(void) 574 { 575 bd_t *bd = gd->bd; 576 577 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ 578 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ 579 #if defined(CONFIG_CPM2) 580 bd->bi_cpmfreq = gd->arch.cpm_clk; 581 bd->bi_brgfreq = gd->arch.brg_clk; 582 bd->bi_sccfreq = gd->arch.scc_clk; 583 bd->bi_vco = gd->arch.vco_out; 584 #endif /* CONFIG_CPM2 */ 585 #if defined(CONFIG_MPC512X) 586 bd->bi_ipsfreq = gd->arch.ips_clk; 587 #endif /* CONFIG_MPC512X */ 588 #if defined(CONFIG_MPC5xxx) 589 bd->bi_ipbfreq = gd->arch.ipb_clk; 590 bd->bi_pcifreq = gd->pci_clk; 591 #endif /* CONFIG_MPC5xxx */ 592 #if defined(CONFIG_M68K) && defined(CONFIG_PCI) 593 bd->bi_pcifreq = gd->pci_clk; 594 #endif 595 #if defined(CONFIG_EXTRA_CLOCK) 596 bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */ 597 bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ 598 bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ 599 #endif 600 601 return 0; 602 } 603 #endif 604 605 #ifdef CONFIG_POST 606 static int init_post(void) 607 { 608 post_bootmode_init(); 609 post_run(NULL, POST_ROM | post_bootmode_get(0)); 610 611 return 0; 612 } 613 #endif 614 615 static int reloc_fdt(void) 616 { 617 #ifndef CONFIG_OF_EMBED 618 if (gd->flags & GD_FLG_SKIP_RELOC) 619 return 0; 620 if (gd->new_fdt) { 621 memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); 622 gd->fdt_blob = gd->new_fdt; 623 } 624 #endif 625 626 return 0; 627 } 628 629 static int setup_reloc(void) 630 { 631 if (gd->flags & GD_FLG_SKIP_RELOC) { 632 debug("Skipping relocation due to flag\n"); 633 return 0; 634 } 635 636 #ifdef CONFIG_SYS_TEXT_BASE 637 gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE; 638 #ifdef CONFIG_M68K 639 /* 640 * On all ColdFire arch cpu, monitor code starts always 641 * just after the default vector table location, so at 0x400 642 */ 643 gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400); 644 #endif 645 #endif 646 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); 647 648 debug("Relocation Offset is: %08lx\n", gd->reloc_off); 649 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n", 650 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd), 651 gd->start_addr_sp); 652 653 return 0; 654 } 655 656 #ifdef CONFIG_OF_BOARD_FIXUP 657 static int fix_fdt(void) 658 { 659 return board_fix_fdt((void *)gd->fdt_blob); 660 } 661 #endif 662 663 /* ARM calls relocate_code from its crt0.S */ 664 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 665 !CONFIG_IS_ENABLED(X86_64) 666 667 static int jump_to_copy(void) 668 { 669 if (gd->flags & GD_FLG_SKIP_RELOC) 670 return 0; 671 /* 672 * x86 is special, but in a nice way. It uses a trampoline which 673 * enables the dcache if possible. 674 * 675 * For now, other archs use relocate_code(), which is implemented 676 * similarly for all archs. When we do generic relocation, hopefully 677 * we can make all archs enable the dcache prior to relocation. 678 */ 679 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 680 /* 681 * SDRAM and console are now initialised. The final stack can now 682 * be setup in SDRAM. Code execution will continue in Flash, but 683 * with the stack in SDRAM and Global Data in temporary memory 684 * (CPU cache) 685 */ 686 arch_setup_gd(gd->new_gd); 687 board_init_f_r_trampoline(gd->start_addr_sp); 688 #else 689 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr); 690 #endif 691 692 return 0; 693 } 694 #endif 695 696 /* Record the board_init_f() bootstage (after arch_cpu_init()) */ 697 static int mark_bootstage(void) 698 { 699 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); 700 701 return 0; 702 } 703 704 static int initf_console_record(void) 705 { 706 #if defined(CONFIG_CONSOLE_RECORD) && defined(CONFIG_SYS_MALLOC_F_LEN) 707 return console_record_init(); 708 #else 709 return 0; 710 #endif 711 } 712 713 static int initf_dm(void) 714 { 715 #if defined(CONFIG_DM) && defined(CONFIG_SYS_MALLOC_F_LEN) 716 int ret; 717 718 ret = dm_init_and_scan(true); 719 if (ret) 720 return ret; 721 #endif 722 #ifdef CONFIG_TIMER_EARLY 723 ret = dm_timer_init(); 724 if (ret) 725 return ret; 726 #endif 727 728 return 0; 729 } 730 731 /* Architecture-specific memory reservation */ 732 __weak int reserve_arch(void) 733 { 734 return 0; 735 } 736 737 __weak int arch_cpu_init_dm(void) 738 { 739 return 0; 740 } 741 742 static const init_fnc_t init_sequence_f[] = { 743 setup_mon_len, 744 #ifdef CONFIG_OF_CONTROL 745 fdtdec_setup, 746 #endif 747 #ifdef CONFIG_TRACE 748 trace_early_init, 749 #endif 750 initf_malloc, 751 initf_console_record, 752 #if defined(CONFIG_HAVE_FSP) 753 arch_fsp_init, 754 #endif 755 arch_cpu_init, /* basic arch cpu dependent setup */ 756 mach_cpu_init, /* SoC/machine dependent CPU setup */ 757 initf_dm, 758 arch_cpu_init_dm, 759 mark_bootstage, /* need timer, go after init dm */ 760 #if defined(CONFIG_BOARD_EARLY_INIT_F) 761 board_early_init_f, 762 #endif 763 #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K) 764 /* get CPU and bus clocks according to the environment variable */ 765 get_clocks, /* get CPU and bus clocks (etc.) */ 766 #endif 767 timer_init, /* initialize timer */ 768 #if defined(CONFIG_BOARD_POSTCLK_INIT) 769 board_postclk_init, 770 #endif 771 env_init, /* initialize environment */ 772 init_baud_rate, /* initialze baudrate settings */ 773 serial_init, /* serial communications setup */ 774 console_init_f, /* stage 1 init of console */ 775 display_options, /* say that we are here */ 776 display_text_info, /* show debugging info if required */ 777 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SH) || \ 778 defined(CONFIG_X86) 779 checkcpu, 780 #endif 781 #if defined(CONFIG_DISPLAY_CPUINFO) 782 print_cpuinfo, /* display cpu info (and speed) */ 783 #endif 784 #if defined(CONFIG_DISPLAY_BOARDINFO) 785 show_board_info, 786 #endif 787 INIT_FUNC_WATCHDOG_INIT 788 #if defined(CONFIG_MISC_INIT_F) 789 misc_init_f, 790 #endif 791 INIT_FUNC_WATCHDOG_RESET 792 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) 793 init_func_i2c, 794 #endif 795 #if defined(CONFIG_HARD_SPI) 796 init_func_spi, 797 #endif 798 announce_dram_init, 799 /* TODO: unify all these dram functions? */ 800 #if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \ 801 defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) || \ 802 defined(CONFIG_SH) 803 dram_init, /* configure available RAM banks */ 804 #endif 805 #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K) 806 init_func_ram, 807 #endif 808 #ifdef CONFIG_POST 809 post_init_f, 810 #endif 811 INIT_FUNC_WATCHDOG_RESET 812 #if defined(CONFIG_SYS_DRAM_TEST) 813 testdram, 814 #endif /* CONFIG_SYS_DRAM_TEST */ 815 INIT_FUNC_WATCHDOG_RESET 816 817 #ifdef CONFIG_POST 818 init_post, 819 #endif 820 INIT_FUNC_WATCHDOG_RESET 821 /* 822 * Now that we have DRAM mapped and working, we can 823 * relocate the code and continue running from DRAM. 824 * 825 * Reserve memory at end of RAM for (top down in that order): 826 * - area that won't get touched by U-Boot and Linux (optional) 827 * - kernel log buffer 828 * - protected RAM 829 * - LCD framebuffer 830 * - monitor code 831 * - board info struct 832 */ 833 setup_dest_addr, 834 #if defined(CONFIG_LOGBUFFER) 835 reserve_logbuffer, 836 #endif 837 #ifdef CONFIG_PRAM 838 reserve_pram, 839 #endif 840 reserve_round_4k, 841 #ifdef CONFIG_ARM 842 reserve_mmu, 843 #endif 844 reserve_video, 845 reserve_trace, 846 reserve_uboot, 847 reserve_malloc, 848 reserve_board, 849 setup_machine, 850 reserve_global_data, 851 reserve_fdt, 852 reserve_arch, 853 reserve_stacks, 854 dram_init_banksize, 855 show_dram_config, 856 #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \ 857 defined(CONFIG_SH) 858 setup_board_part1, 859 #endif 860 #if defined(CONFIG_PPC) || defined(CONFIG_M68K) 861 INIT_FUNC_WATCHDOG_RESET 862 setup_board_part2, 863 #endif 864 display_new_sp, 865 #ifdef CONFIG_SYS_EXTBDINFO 866 setup_board_extra, 867 #endif 868 #ifdef CONFIG_OF_BOARD_FIXUP 869 fix_fdt, 870 #endif 871 INIT_FUNC_WATCHDOG_RESET 872 reloc_fdt, 873 setup_reloc, 874 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 875 copy_uboot_to_ram, 876 do_elf_reloc_fixups, 877 clear_bss, 878 #endif 879 #if defined(CONFIG_XTENSA) 880 clear_bss, 881 #endif 882 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 883 !CONFIG_IS_ENABLED(X86_64) 884 jump_to_copy, 885 #endif 886 NULL, 887 }; 888 889 void board_init_f(ulong boot_flags) 890 { 891 #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA 892 /* 893 * For some architectures, global data is initialized and used before 894 * calling this function. The data should be preserved. For others, 895 * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack 896 * here to host global data until relocation. 897 */ 898 gd_t data; 899 900 gd = &data; 901 902 /* 903 * Clear global data before it is accessed at debug print 904 * in initcall_run_list. Otherwise the debug print probably 905 * get the wrong value of gd->have_console. 906 */ 907 zero_global_data(); 908 #endif 909 910 gd->flags = boot_flags; 911 gd->have_console = 0; 912 913 if (initcall_run_list(init_sequence_f)) 914 hang(); 915 916 #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \ 917 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) 918 /* NOTREACHED - jump_to_copy() does not return */ 919 hang(); 920 #endif 921 } 922 923 #if defined(CONFIG_X86) || defined(CONFIG_ARC) 924 /* 925 * For now this code is only used on x86. 926 * 927 * init_sequence_f_r is the list of init functions which are run when 928 * U-Boot is executing from Flash with a semi-limited 'C' environment. 929 * The following limitations must be considered when implementing an 930 * '_f_r' function: 931 * - 'static' variables are read-only 932 * - Global Data (gd->xxx) is read/write 933 * 934 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if 935 * supported). It _should_, if possible, copy global data to RAM and 936 * initialise the CPU caches (to speed up the relocation process) 937 * 938 * NOTE: At present only x86 uses this route, but it is intended that 939 * all archs will move to this when generic relocation is implemented. 940 */ 941 static const init_fnc_t init_sequence_f_r[] = { 942 #if !CONFIG_IS_ENABLED(X86_64) 943 init_cache_f_r, 944 #endif 945 946 NULL, 947 }; 948 949 void board_init_f_r(void) 950 { 951 if (initcall_run_list(init_sequence_f_r)) 952 hang(); 953 954 /* 955 * The pre-relocation drivers may be using memory that has now gone 956 * away. Mark serial as unavailable - this will fall back to the debug 957 * UART if available. 958 */ 959 gd->flags &= ~GD_FLG_SERIAL_READY; 960 961 /* 962 * U-Boot has been copied into SDRAM, the BSS has been cleared etc. 963 * Transfer execution from Flash to RAM by calculating the address 964 * of the in-RAM copy of board_init_r() and calling it 965 */ 966 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr); 967 968 /* NOTREACHED - board_init_r() does not return */ 969 hang(); 970 } 971 #endif /* CONFIG_X86 */ 972