1 /* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11 12 #define MACTEST_C 13 14 #include "swfunc.h" 15 #include "comminf.h" 16 #include <command.h> 17 #include <common.h> 18 #include <malloc.h> 19 #include <net.h> 20 #include <post.h> 21 #include "mem_io.h" 22 23 #include "phy_api.h" 24 #include "mac_api.h" 25 26 #define ARGV_MAC_IDX 1 27 #define ARGV_MDIO_IDX 2 28 #define ARGV_SPEED 3 29 #define ARGV_CTRL 4 30 #define ARGV_LOOP 5 31 #define ARGV_TEST_MODE 6 32 #define ARGV_PHY_ADDR 7 33 #define ARGV_TIMING_MARGIN 8 34 35 36 uint8_t __attribute__ ((aligned (1024*1024))) tdes_buf[TDES_SIZE]; 37 uint8_t __attribute__ ((aligned (1024*1024))) rdes_buf[RDES_SIZE]; 38 uint8_t __attribute__ ((aligned (1024*1024))) dma_buf[DMA_BUF_SIZE]; 39 40 struct mac_ctrl_desc { 41 uint32_t base_reset_assert; 42 uint32_t bit_reset_assert; 43 uint32_t base_reset_deassert; 44 uint32_t bit_reset_deassert; 45 46 uint32_t base_clk_stop; 47 uint32_t bit_clk_stop; 48 uint32_t base_clk_start; 49 uint32_t bit_clk_start; 50 }; 51 52 static const uint32_t timeout_th_tbl[3] = { 53 TIME_OUT_Des_1G, TIME_OUT_Des_100M, TIME_OUT_Des_10M}; 54 #if defined(CONFIG_ASPEED_AST2600) 55 const uint32_t mac_base_lookup_tbl[4] = {MAC1_BASE, MAC2_BASE, MAC3_BASE, 56 MAC4_BASE}; 57 const uint32_t mdio_base_lookup_tbl[4] = {MDIO0_BASE, MDIO1_BASE, MDIO2_BASE, 58 MDIO3_BASE}; 59 const struct mac_ctrl_desc mac_ctrl_lookup_tbl[4] = { 60 { 61 .base_reset_assert = 0x40, .bit_reset_assert = BIT(11), 62 .base_reset_deassert = 0x44,.bit_reset_deassert = BIT(11), 63 .base_clk_stop = 0x80, .bit_clk_stop = BIT(20), 64 .base_clk_start = 0x84, .bit_clk_start = BIT(20), 65 }, 66 { 67 .base_reset_assert = 0x40, .bit_reset_assert = BIT(12), 68 .base_reset_deassert = 0x44,.bit_reset_deassert = BIT(12), 69 .base_clk_stop = 0x80, .bit_clk_stop = BIT(21), 70 .base_clk_start = 0x84,.bit_clk_start = BIT(21), 71 }, 72 { 73 .base_reset_assert = 0x50, .bit_reset_assert = BIT(20), 74 .base_reset_deassert = 0x54,.bit_reset_deassert = BIT(20), 75 .base_clk_stop = 0x90, .bit_clk_stop = BIT(20), 76 .base_clk_start = 0x94, .bit_clk_start = BIT(20), 77 }, 78 { 79 .base_reset_assert = 0x50, .bit_reset_assert = BIT(21), 80 .base_reset_deassert = 0x54,.bit_reset_deassert = BIT(21), 81 .base_clk_stop = 0x90, .bit_clk_stop = BIT(21), 82 .base_clk_start = 0x94,.bit_clk_start = BIT(21), 83 } 84 }; 85 #else 86 const uint32_t mac_base_lookup_tbl[2] = {MAC1_BASE, MAC2_BASE}; 87 const uint32_t mdio_base_lookup_tbl[2] = {MDIO0_BASE, MDIO1_BASE}; 88 const struct mac_ctrl_desc mac_ctrl_lookup_tbl[2] = { 89 { 90 .base_reset_assert = 0x04, .bit_reset_assert = 11, 91 .base_reset_deassert = 0x04,.bit_reset_deassert = 11, 92 .base_clk_stop = 0x0c, .bit_clk_stop = 20, 93 .base_clk_start = 0x0c, .bit_clk_start = 20, 94 }, 95 { 96 .base_reset_assert = 0x04, .bit_reset_assert = 12, 97 .base_reset_deassert = 0x04,.bit_reset_deassert = 12, 98 .base_clk_stop = 0x0c, .bit_clk_stop = 21, 99 .base_clk_start = 0x0c,.bit_clk_start = 21, 100 } 101 }; 102 #endif 103 104 void Print_Header(MAC_ENGINE *p_eng, uint8_t option) 105 { 106 if (p_eng->run.speed_sel[0]) { 107 PRINTF(option, " 1G "); 108 } else if (p_eng->run.speed_sel[1]) { 109 PRINTF(option, " 100M "); 110 } else { 111 PRINTF(option, " 10M "); 112 } 113 114 switch (p_eng->arg.test_mode) { 115 case 0: 116 PRINTF(option, "TX/RX delay margin check\n"); 117 break; 118 case 1: 119 PRINTF(option, "TX/RX delay scan\n"); 120 break; 121 case 2: 122 PRINTF(option, "TX/RX delay and IO driving scan\n"); 123 break; 124 case 3: 125 PRINTF(option, "TX frame - ARP\n"); 126 break; 127 case 4: 128 PRINTF(option, "TX frame - random\n"); 129 break; 130 case 5: 131 PRINTF(option, "TX frame - 0x%08x\n", p_eng->arg.user_def_val); 132 break; 133 } 134 } 135 136 static void print_arg_test_mode(MAC_ENGINE *p_eng) 137 { 138 uint8_t item[32] = "test_mode[dec]"; 139 140 if (p_eng->arg.run_mode == MODE_NCSI) { 141 printf("%20s| 0: NCSI configuration with " 142 "Disable_Channel request\n", item); 143 printf("%20s| (default:%3d)\n", "", DEF_GTESTMODE); 144 printf("%20s| 1: TX/RX delay scan\n", ""); 145 printf("%20s| 2: TX/RX delay and IO driving scan\n", ""); 146 printf("%20s| 3: NCSI configuration without " 147 "Disable_Channel request\n", ""); 148 } else { 149 printf("%20s| (default:%3d)\n", item, DEF_GTESTMODE); 150 printf("%20s| 0: TX/RX delay margin check\n", ""); 151 printf("%20s| 1: TX/RX delay scan\n", ""); 152 printf("%20s| 2: TX/RX delay and IO driving scan\n", ""); 153 printf("%20s| 3: TX frame - ARP\n", ""); 154 printf("%20s| 4: TX frame - random\n", ""); 155 printf("%20s| 5: TX frame - user defined (default:0x%8x)\n", "", 156 DEF_GUSER_DEF_PACKET_VAL); 157 } 158 } 159 160 static void print_arg_phy_addr(MAC_ENGINE *p_eng) 161 { 162 uint8_t item[32] = "phy_addr[dec]"; 163 164 printf("%20s| 0~31: PHY Address (default:%d)\n", item, DEF_GPHY_ADR); 165 } 166 167 static void print_arg_ieee_select(MAC_ENGINE *p_eng) 168 { 169 uint8_t item[32] = "IEEE packet select"; 170 171 printf("%20s| 0/1/2 (default:0) only for test_mode 3,4,5)\n", item); 172 } 173 174 static void print_arg_delay_scan_range(MAC_ENGINE *p_eng) 175 { 176 uint8_t item[32] = "TX/RX delay margin"; 177 178 printf("%20s| 1/2/3/... (default:%d) only for test_mode 0\n", item, 179 DEF_GIOTIMINGBUND); 180 printf("%20s| check range = (orig - margin) ~ (orig + margin)\n", ""); 181 print_arg_ieee_select(p_eng); 182 } 183 184 static void print_arg_channel_num(MAC_ENGINE *p_eng) 185 { 186 uint8_t item[32] = "channel_num[dec]"; 187 188 printf("%20s| 1~32: Total Number of NCSI Channel (default:%d)\n", item, 189 DEF_GCHANNEL2NUM); 190 } 191 192 static void print_arg_package_num(MAC_ENGINE *p_eng) 193 { 194 uint8_t item[32] = "package_num[dec]"; 195 196 printf("%20s| 1~ 8: Total Number of NCSI Package (default:%d)\n", item, 197 DEF_GPACKAGE2NUM); 198 } 199 200 static void print_arg_loop(MAC_ENGINE *p_eng) 201 { 202 uint8_t item[32] = "loop_max[dec]"; 203 204 printf("%20s| 1G : (default:%3d)\n", item, DEF_GLOOP_MAX * 20); 205 printf("%20s| 100M: (default:%3d)\n", "", DEF_GLOOP_MAX * 2); 206 printf("%20s| 10M : (default:%3d)\n", "", DEF_GLOOP_MAX); 207 } 208 209 static void print_arg_ctrl(MAC_ENGINE *p_eng) 210 { 211 uint8_t item[32] = "ctrl[hex]"; 212 213 printf("%20s| default : 0x%03x\n", item, DEF_GCTRL); 214 printf("%20s| bit0 : skip PHY init/deinit\n", ""); 215 printf("%20s| bit1 : skip PHY deinit\n", ""); 216 printf("%20s| bit2 : skip PHY ID check\n", ""); 217 printf("%20s| bit3 : reserved\n", ""); 218 printf("%20s| bit4 : PHY internal loopback\n", ""); 219 printf("%20s| bit5 : MAC internal loopback\n", ""); 220 printf("%20s| bit7~6 : reserved\n", ""); 221 printf("%20s| bit8 : RMII 50MHz Output enable\n", ""); 222 printf("%20s| bit9 : RMII REFCLK pin input enable\n", ""); 223 printf("%20s| bit10 : inverse RGMII RXCLK\n", ""); 224 printf("%20s| bit11 : reserved\n", ""); 225 printf("%20s| bit12 : TX single packet for each test point\n", ""); 226 printf("%20s| bit13 : full range scan\n", ""); 227 printf("%20s| bit15~14 : reserved\n", ""); 228 printf("%20s| bit16 : NCSI verbose log\n", ""); 229 printf("%20s| bit17 : NCSI skip RX error\n", ""); 230 printf("%20s| bit31~18 : reserved\n", ""); 231 } 232 233 static void print_arg_speed(MAC_ENGINE *p_eng) 234 { 235 uint8_t item[32] = "speed[hex]"; 236 237 printf("%20s| bit[0]->1G bit[1]->100M bit[2]->10M " 238 "(default:0x%02lx)\n", 239 item, DEF_GSPEED); 240 } 241 242 static void print_arg_mdio_idx(MAC_ENGINE *p_eng) 243 { 244 uint8_t item[32] = "mdio_idx[dec]"; 245 246 printf("%20s| 0->MDIO1 1->MDIO2", item); 247 248 if (p_eng->env.mac_num > 2) { 249 printf(" 2->MDIO3 3->MDIO4"); 250 } 251 printf("\n"); 252 } 253 254 static void print_arg_mac_idx(MAC_ENGINE *p_eng) 255 { 256 uint8_t item[32] = "mac_idx[dec]"; 257 258 printf("%20s| 0->MAC1 1->MAC2", item); 259 260 if (p_eng->env.mac_num > 2) { 261 printf(" 2->MAC3 3->MAC4"); 262 } 263 printf("\n"); 264 } 265 static void print_legend(void) 266 { 267 printf("Legend:\n"); 268 printf(" o : OK\n"); 269 printf(" x : CRC error\n"); 270 printf(" . : packet not found\n"); 271 printf(" System default setting\n"); 272 printf(" O : OK\n"); 273 printf(" X : CRC error\n"); 274 printf(" * : packet not found\n"); 275 } 276 static void print_usage(MAC_ENGINE *p_eng) 277 { 278 if (MODE_DEDICATED == p_eng->arg.run_mode) { 279 printf("mactest <mac_idx> <mdio_idx> <speed> <ctrl> <loop_max> <test " 280 "mode> <phy addr> <margin / IEEE select> <user data>\n"); 281 print_arg_mac_idx(p_eng); 282 print_arg_mdio_idx(p_eng); 283 print_arg_speed(p_eng); 284 print_arg_ctrl(p_eng); 285 print_arg_loop(p_eng); 286 print_arg_test_mode(p_eng); 287 print_arg_phy_addr(p_eng); 288 print_arg_delay_scan_range(p_eng); 289 } else if (MODE_NCSI == p_eng->arg.run_mode) { 290 printf("ncsitest <idx> <packet num> <channel num> <test mode>" 291 "<margin> <ctrl> <ARP num>\n"); 292 print_arg_mac_idx(p_eng); 293 print_arg_package_num(p_eng); 294 print_arg_channel_num(p_eng); 295 print_arg_test_mode(p_eng); 296 print_arg_delay_scan_range(p_eng); 297 print_arg_ctrl(p_eng); 298 } else { 299 printf("unknown run mode\n"); 300 } 301 } 302 303 static void push_reg(MAC_ENGINE *p_eng) 304 { 305 /* SCU delay settings */ 306 p_eng->io.mac12_1g_delay.value.w = readl(p_eng->io.mac12_1g_delay.addr); 307 p_eng->io.mac12_100m_delay.value.w = readl(p_eng->io.mac12_100m_delay.addr); 308 p_eng->io.mac12_10m_delay.value.w = readl(p_eng->io.mac12_10m_delay.addr); 309 310 #ifdef CONFIG_ASPEED_AST2600 311 p_eng->io.mac34_1g_delay.value.w = readl(p_eng->io.mac34_1g_delay.addr); 312 p_eng->io.mac34_100m_delay.value.w = readl(p_eng->io.mac34_100m_delay.addr); 313 p_eng->io.mac34_10m_delay.value.w = readl(p_eng->io.mac34_10m_delay.addr); 314 315 p_eng->io.mac34_drv_reg.value.w = readl(p_eng->io.mac34_drv_reg.addr); 316 #else 317 p_eng->io.mac12_drv_reg.value.w = readl(p_eng->io.mac12_drv_reg.addr); 318 #endif 319 320 /* MAC registers */ 321 p_eng->reg.maccr.w = mac_reg_read(p_eng, 0x50); 322 323 p_eng->reg.mac_madr = mac_reg_read(p_eng, 0x08); 324 p_eng->reg.mac_ladr = mac_reg_read(p_eng, 0x0c); 325 p_eng->reg.mac_fear = mac_reg_read(p_eng, 0x40); 326 } 327 328 static void pop_reg(MAC_ENGINE *p_eng) 329 { 330 /* SCU delay settings */ 331 writel(p_eng->io.mac12_1g_delay.value.w, p_eng->io.mac12_1g_delay.addr); 332 writel(p_eng->io.mac12_100m_delay.value.w, p_eng->io.mac12_100m_delay.addr); 333 writel(p_eng->io.mac12_10m_delay.value.w, p_eng->io.mac12_10m_delay.addr); 334 335 #ifdef CONFIG_ASPEED_AST2600 336 writel(p_eng->io.mac34_1g_delay.value.w, p_eng->io.mac34_1g_delay.addr); 337 writel(p_eng->io.mac34_100m_delay.value.w, p_eng->io.mac34_100m_delay.addr); 338 writel(p_eng->io.mac34_10m_delay.value.w, p_eng->io.mac34_10m_delay.addr); 339 340 writel(p_eng->io.mac34_drv_reg.value.w, p_eng->io.mac34_drv_reg.addr); 341 #else 342 writel(p_eng->io.mac12_drv_reg.value.w, p_eng->io.mac12_drv_reg.addr); 343 #endif 344 345 /* MAC registers */ 346 mac_reg_write(p_eng, 0x50, p_eng->reg.maccr.w); 347 mac_reg_write(p_eng, 0x08, p_eng->reg.mac_madr); 348 mac_reg_write(p_eng, 0x0c, p_eng->reg.mac_ladr); 349 mac_reg_write(p_eng, 0x40, p_eng->reg.mac_fear); 350 } 351 352 static void finish_close(MAC_ENGINE *p_eng) 353 { 354 nt_log_func_name(); 355 pop_reg(p_eng); 356 } 357 358 char finish_check(MAC_ENGINE *p_eng, int value) 359 { 360 nt_log_func_name(); 361 362 if (p_eng->arg.run_mode == MODE_DEDICATED) { 363 if (p_eng->dat.FRAME_LEN) 364 free(p_eng->dat.FRAME_LEN); 365 366 if (p_eng->dat.wp_lst) 367 free(p_eng->dat.wp_lst); 368 } 369 370 p_eng->flg.Err_Flag = p_eng->flg.Err_Flag | value; 371 372 if (DbgPrn_ErrFlg) 373 printf("\nErr_Flag: [%08x]\n", p_eng->flg.Err_Flag); 374 375 if (!p_eng->run.tm_tx_only) 376 FPri_ErrFlag(p_eng, FP_LOG); 377 378 if (p_eng->run.TM_IOTiming) 379 FPri_ErrFlag(p_eng, FP_IO); 380 381 FPri_ErrFlag(p_eng, STD_OUT); 382 383 if (!p_eng->run.tm_tx_only) 384 FPri_End(p_eng, FP_LOG); 385 386 if (p_eng->run.TM_IOTiming) 387 FPri_End(p_eng, FP_IO); 388 389 FPri_End(p_eng, STD_OUT); 390 391 if (!p_eng->run.tm_tx_only) 392 FPri_RegValue(p_eng, FP_LOG); 393 if (p_eng->run.TM_IOTiming) 394 FPri_RegValue(p_eng, FP_IO); 395 396 finish_close(p_eng); 397 398 if (p_eng->flg.Err_Flag) { 399 return (1); 400 } else { 401 return (0); 402 } 403 } 404 405 static uint32_t check_test_mode(MAC_ENGINE *p_eng) 406 { 407 if (p_eng->arg.run_mode == MODE_NCSI ) { 408 switch (p_eng->arg.test_mode) { 409 case 0: 410 break; 411 case 1: 412 p_eng->run.TM_IOTiming = 1; 413 break; 414 case 2: 415 p_eng->run.TM_IOTiming = 1; 416 p_eng->run.TM_IOStrength = 1; 417 break; 418 case 3: 419 p_eng->run.TM_NCSI_DiSChannel = 0; 420 break; 421 default: 422 printf("Error test_mode!!!\n"); 423 print_arg_test_mode(p_eng); 424 return (1); 425 } 426 } else { 427 switch (p_eng->arg.test_mode) { 428 case 0: 429 break; 430 case 1: 431 p_eng->run.TM_IOTiming = 1; 432 break; 433 case 2: 434 p_eng->run.TM_IOTiming = 1; 435 p_eng->run.TM_IOStrength = 1; 436 break; 437 case 3: 438 /* TX ARP frame */ 439 p_eng->run.TM_RxDataEn = 0; 440 p_eng->run.tm_tx_only = 1; 441 p_eng->run.TM_IEEE = 0; 442 break; 443 case 4: 444 case 5: 445 p_eng->run.TM_RxDataEn = 0; 446 p_eng->run.tm_tx_only = 1; 447 p_eng->run.TM_IEEE = 1; 448 break; 449 default: 450 printf("Error test_mode!!!\n"); 451 print_arg_test_mode(p_eng); 452 return (1); 453 } 454 } 455 456 if (0 == p_eng->run.TM_IOStrength) { 457 p_eng->io.drv_upper_bond = 0; 458 } 459 return 0; 460 } 461 462 /** 463 * @brief enable/disable MAC 464 * @param[in] p_eng - MAC_ENGINE 465 * 466 * AST2600 uses synchronous reset scheme, so the bits for reset assert and 467 * deassert are the same 468 * e.g. MAC#1: SCU04[11] = 1 --> MAC#1 reset assert 469 * = 0 --> MAC#1 reset de-assert 470 * 471 * AST2600 uses asynchronous reset scheme, so the bits for reset assert and 472 * deassert are different 473 * e.g. MAC#1: SCU40[11] = 1 --> MAC#1 reset assert 474 * SCU44[11] = 1 --> MAC#1 reset de-assert 475 * 476 * The same design concept is also adopted on clock stop/start. 477 */ 478 void scu_disable_mac(MAC_ENGINE *p_eng) 479 { 480 uint32_t mac_idx = p_eng->run.mac_idx; 481 const struct mac_ctrl_desc *p_mac = &mac_ctrl_lookup_tbl[mac_idx]; 482 uint32_t reg; 483 484 debug("MAC%d:reset assert=0x%02x[%08x] deassert=0x%02x[%08x]\n", 485 mac_idx, p_mac->base_reset_assert, p_mac->bit_reset_assert, 486 p_mac->base_reset_deassert, p_mac->bit_reset_deassert); 487 debug("MAC%d:clock stop=0x%02x[%08x] start=0x%02x[%08x]\n", mac_idx, 488 p_mac->base_clk_stop, p_mac->bit_clk_stop, p_mac->base_clk_start, 489 p_mac->bit_clk_start); 490 491 reg = SCU_RD(p_mac->base_reset_assert); 492 debug("reset reg: 0x%08x\n", reg); 493 reg |= p_mac->bit_reset_assert; 494 debug("reset reg: 0x%08x\n", reg); 495 SCU_WR(reg, p_mac->base_reset_assert); 496 /* issue a dummy read to ensure command is in order */ 497 reg = SCU_RD(p_mac->base_reset_assert); 498 499 reg = SCU_RD(p_mac->base_clk_stop); 500 debug("clock reg: 0x%08x\n", reg); 501 reg |= p_mac->bit_clk_stop; 502 debug("clock reg: 0x%08x\n", reg); 503 SCU_WR(reg, p_mac->base_clk_stop); 504 /* issue a dummy read to ensure command is in order */ 505 reg = SCU_RD(p_mac->base_clk_stop); 506 } 507 508 void scu_enable_mac(MAC_ENGINE *p_eng) 509 { 510 uint32_t mac_idx = p_eng->run.mac_idx; 511 const struct mac_ctrl_desc *p_mac = &mac_ctrl_lookup_tbl[mac_idx]; 512 uint32_t reg; 513 514 debug("MAC%d:reset assert=0x%02x[%08x] deassert=0x%02x[%08x]\n", 515 mac_idx, p_mac->base_reset_assert, p_mac->bit_reset_assert, 516 p_mac->base_reset_deassert, p_mac->bit_reset_deassert); 517 debug("MAC%d:clock stop=0x%02x[%08x] start=0x%02x[%08x]\n", mac_idx, 518 p_mac->base_clk_stop, p_mac->bit_clk_stop, p_mac->base_clk_start, 519 p_mac->bit_clk_start); 520 521 #ifdef CONFIG_ASPEED_AST2600 522 reg = SCU_RD(p_mac->base_reset_deassert); 523 debug("reset reg: 0x%08x\n", reg); 524 reg |= p_mac->bit_reset_deassert; 525 debug("reset reg: 0x%08x\n", reg); 526 SCU_WR(reg, p_mac->base_reset_deassert); 527 /* issue a dummy read to ensure command is in order */ 528 reg = SCU_RD(p_mac->base_reset_deassert); 529 530 reg = SCU_RD(p_mac->base_clk_start); 531 debug("clock reg: 0x%08x\n", reg); 532 reg |= p_mac->bit_clk_start; 533 debug("clock reg: 0x%08x\n", reg); 534 SCU_WR(reg, p_mac->base_clk_start); 535 /* issue a dummy read to ensure command is in order */ 536 reg = SCU_RD(p_mac->base_clk_start); 537 #else 538 reg = SCU_RD(p_mac->base_reset_deassert); 539 reg &= ~p_mac->bit_reset_deassert; 540 SCU_WR(reg, p_mac->base_reset_deassert); 541 /* issue a dummy read to ensure command is in order */ 542 reg = SCU_RD(p_mac->base_reset_deassert); 543 544 reg = SCU_RD(p_mac->base_clk_start); 545 reg &= ~p_mac->bit_clk_start; 546 SCU_WR(reg, p_mac->base_clk_start); 547 /* issue a dummy read to ensure command is in order */ 548 reg = SCU_RD(p_mac->base_clk_start); 549 #endif 550 } 551 552 /** 553 * @brief setup mdc/mdio pinmix 554 * @todo push/pop pinmux registers 555 */ 556 void scu_set_pinmux(MAC_ENGINE *p_eng) 557 { 558 uint32_t reg; 559 nt_log_func_name(); 560 561 #ifdef CONFIG_ASPEED_AST2600 562 /* MDC/MDIO pinmux */ 563 switch (p_eng->run.mdio_idx) { 564 case 0: 565 reg = SCU_RD(0x430) | GENMASK(17, 16); 566 SCU_WR(reg, 0x430); 567 break; 568 case 1: 569 reg = SCU_RD(0x470) & ~GENMASK(13, 12); 570 SCU_WR(reg, 0x470); 571 reg = SCU_RD(0x410) | GENMASK(13, 12); 572 SCU_WR(reg, 0x410); 573 break; 574 case 2: 575 reg = SCU_RD(0x470) & ~GENMASK(1, 0); 576 SCU_WR(reg, 0x470); 577 reg = SCU_RD(0x410) | GENMASK(1, 0); 578 SCU_WR(reg, 0x410); 579 break; 580 case 3: 581 reg = SCU_RD(0x470) & ~GENMASK(3, 2); 582 SCU_WR(reg, 0x470); 583 reg = SCU_RD(0x410) | GENMASK(3, 2); 584 SCU_WR(reg, 0x410); 585 break; 586 default: 587 printf("%s:undefined MDIO idx %d\n", __func__, 588 p_eng->run.mdio_idx); 589 } 590 591 switch (p_eng->run.mac_idx) { 592 case 0: 593 #ifdef CONFIG_FPGA_ASPEED 594 setbits_le32(SCU_BASE + 0x410, BIT(4)); 595 #else 596 setbits_le32(SCU_BASE + 0x400, GENMASK(11, 0)); 597 setbits_le32(SCU_BASE + 0x410, BIT(4)); 598 clrbits_le32(SCU_BASE + 0x470, BIT(4)); 599 #endif 600 break; 601 case 1: 602 setbits_le32(SCU_BASE + 0x400, GENMASK(23, 12)); 603 setbits_le32(SCU_BASE + 0x410, BIT(5)); 604 clrbits_le32(SCU_BASE + 0x470, BIT(5)); 605 break; 606 case 2: 607 setbits_le32(SCU_BASE + 0x410, GENMASK(27, 16)); 608 setbits_le32(SCU_BASE + 0x410, BIT(6)); 609 clrbits_le32(SCU_BASE + 0x470, BIT(6)); 610 break; 611 case 3: 612 clrbits_le32(SCU_BASE + 0x410, GENMASK(31, 28)); 613 setbits_le32(SCU_BASE + 0x4b0, GENMASK(31, 28)); 614 clrbits_le32(SCU_BASE + 0x474, GENMASK(7, 0)); 615 clrbits_le32(SCU_BASE + 0x414, GENMASK(7, 0)); 616 setbits_le32(SCU_BASE + 0x4b4, GENMASK(7, 0)); 617 setbits_le32(SCU_BASE + 0x410, BIT(7)); 618 clrbits_le32(SCU_BASE + 0x470, BIT(7)); 619 break; 620 621 } 622 623 debug("SCU410: %08x %08x %08x %08x\n", SCU_RD(0x410), SCU_RD(0x414), SCU_RD(0x418), SCU_RD(0x41c)); 624 debug("SCU430: %08x %08x %08x %08x\n", SCU_RD(0x430), SCU_RD(0x434), SCU_RD(0x438), SCU_RD(0x43c)); 625 debug("SCU470: %08x %08x %08x %08x\n", SCU_RD(0x470), SCU_RD(0x474), SCU_RD(0x478), SCU_RD(0x47c)); 626 debug("SCU4b0: %08x %08x %08x %08x\n", SCU_RD(0x4b0), SCU_RD(0x4b4), SCU_RD(0x4b8), SCU_RD(0x4bc)); 627 #else 628 /* MDC/MDIO pinmux */ 629 if (p_eng->run.mdio_idx == 0) { 630 setbits_le32(SCU_BASE + 88, GENMASK(31, 30)); 631 } else { 632 clrsetbits_le32(SCU_BASE + 90, BIT(6), BIT(2)); 633 } 634 635 /* enable MAC#nLINK pin */ 636 setbits_le32(SCU_BASE + 80, BIT(p_eng->run.mac_idx)); 637 #endif 638 } 639 640 static uint32_t check_mac_idx(MAC_ENGINE *p_eng) 641 { 642 /* check if legal run_idx */ 643 if (p_eng->arg.mac_idx > p_eng->env.mac_num - 1) { 644 printf("invalid run_idx = %d\n", p_eng->arg.mac_idx); 645 return 1; 646 } 647 648 return 0; 649 } 650 651 static void calc_loop_check_num(MAC_ENGINE *p_eng) 652 { 653 nt_log_func_name(); 654 655 if (p_eng->run.IO_MrgChk || 656 (p_eng->arg.run_speed == SET_1G_100M_10MBPS) || 657 (p_eng->arg.run_speed == SET_100M_10MBPS)) { 658 p_eng->run.LOOP_CheckNum = p_eng->run.loop_max; 659 } else { 660 switch (p_eng->arg.run_speed) { 661 case SET_1GBPS: 662 p_eng->run.CheckBuf_MBSize = MOVE_DATA_MB_SEC; 663 break; 664 case SET_100MBPS: 665 p_eng->run.CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 3); 666 break; 667 case SET_10MBPS: 668 p_eng->run.CheckBuf_MBSize = (MOVE_DATA_MB_SEC >> 6); 669 break; 670 } 671 p_eng->run.LOOP_CheckNum = 672 (p_eng->run.CheckBuf_MBSize / 673 (((p_eng->dat.Des_Num * DMA_PakSize) >> 20) + 1)); 674 } 675 } 676 677 static uint32_t setup_running(MAC_ENGINE *p_eng) 678 { 679 uint32_t n_desp_min; 680 681 if (0 != check_mac_idx(p_eng)) { 682 return 1; 683 } 684 p_eng->run.mac_idx = p_eng->arg.mac_idx; 685 p_eng->run.mac_base = mac_base_lookup_tbl[p_eng->run.mac_idx]; 686 687 p_eng->run.mdio_idx = p_eng->arg.mdio_idx; 688 p_eng->run.mdio_base = mdio_base_lookup_tbl[p_eng->run.mdio_idx]; 689 690 p_eng->run.is_rgmii = p_eng->env.is_1g_valid[p_eng->run.mac_idx]; 691 692 /* 693 * FIXME: too ugly... 694 * check if legal speed setup 695 * */ 696 switch (p_eng->arg.run_speed) { 697 case SET_1GBPS: 698 p_eng->run.speed_cfg[0] = 1; 699 p_eng->run.speed_cfg[1] = 0; 700 p_eng->run.speed_cfg[2] = 0; 701 if (0 == p_eng->env.is_1g_valid[p_eng->run.mac_idx]) { 702 printf("MAC%d doesn't support 1G\n", 703 p_eng->run.mac_idx); 704 return 1; 705 } 706 break; 707 case SET_100MBPS: 708 p_eng->run.speed_cfg[0] = 0; 709 p_eng->run.speed_cfg[1] = 1; 710 p_eng->run.speed_cfg[2] = 0; 711 break; 712 case SET_10MBPS: 713 p_eng->run.speed_cfg[0] = 0; 714 p_eng->run.speed_cfg[1] = 0; 715 p_eng->run.speed_cfg[2] = 1; 716 break; 717 case SET_1G_100M_10MBPS: 718 p_eng->run.speed_cfg[0] = 1; 719 p_eng->run.speed_cfg[1] = 1; 720 p_eng->run.speed_cfg[2] = 1; 721 break; 722 case SET_100M_10MBPS: 723 p_eng->run.speed_cfg[0] = 0; 724 p_eng->run.speed_cfg[1] = 1; 725 p_eng->run.speed_cfg[2] = 1; 726 break; 727 default: 728 printf("Error speed!!!\n"); 729 print_arg_speed(p_eng); 730 return (1); 731 } 732 733 if (p_eng->arg.run_mode == MODE_NCSI) { 734 /* 735 * [Arg]check GPackageTolNum 736 * [Arg]check GChannelTolNum 737 */ 738 if ((p_eng->arg.GPackageTolNum < 1) || 739 (p_eng->arg.GPackageTolNum > 8)) { 740 print_arg_package_num(p_eng); 741 return (1); 742 } 743 if ((p_eng->arg.GChannelTolNum < 1) || 744 (p_eng->arg.GChannelTolNum > 32)) { 745 print_arg_channel_num(p_eng); 746 return (1); 747 } 748 } else { 749 /* [Arg]check ctrl */ 750 if (p_eng->arg.ctrl.w & 0xfffc0000) { 751 print_arg_ctrl(p_eng); 752 return (1); 753 } 754 755 if (p_eng->arg.phy_addr > 31) { 756 printf("Error phy_adr!!!\n"); 757 print_arg_phy_addr(p_eng); 758 return (1); 759 } 760 761 if (0 == p_eng->arg.loop_max) { 762 switch (p_eng->arg.run_speed) { 763 case SET_1GBPS: 764 p_eng->arg.loop_max = DEF_GLOOP_MAX * 20; 765 break; 766 case SET_100MBPS: 767 p_eng->arg.loop_max = DEF_GLOOP_MAX * 2; 768 break; 769 case SET_10MBPS: 770 p_eng->arg.loop_max = DEF_GLOOP_MAX; 771 break; 772 case SET_1G_100M_10MBPS: 773 p_eng->arg.loop_max = DEF_GLOOP_MAX * 20; 774 break; 775 case SET_100M_10MBPS: 776 p_eng->arg.loop_max = DEF_GLOOP_MAX * 2; 777 break; 778 } 779 } 780 } 781 782 if (0 != check_test_mode(p_eng)) { 783 return 1; 784 } 785 786 if (p_eng->run.tm_tx_only) { 787 p_eng->run.ieee_sel = p_eng->arg.ieee_sel; 788 p_eng->run.delay_margin = 0; 789 } else { 790 p_eng->run.ieee_sel = 0; 791 p_eng->run.delay_margin = p_eng->arg.delay_scan_range; 792 #if 0 793 if (p_eng->run.delay_margin == 0) { 794 printf("Error IO margin!!!\n"); 795 print_arg_delay_scan_range(p_eng); 796 return(1); 797 } 798 #endif 799 } 800 801 if (!p_eng->env.is_1g_valid[p_eng->run.mac_idx]) 802 p_eng->run.speed_cfg[ 0 ] = 0; 803 804 805 if (p_eng->arg.run_mode == MODE_NCSI) { 806 if (p_eng->run.is_rgmii) { 807 printf("\nNCSI must be RMII interface !!!\n"); 808 return (finish_check(p_eng, Err_Flag_MACMode)); 809 } 810 811 #ifdef CONFIG_ASPEED_AST2600 812 /** 813 * NCSI needs for 3.3V IO voltage but MAC#1 & MAC#2 only 814 * support 1.8V. So NCSI can only runs on MAC#3 or MAC#4 815 */ 816 if (p_eng->run.mac_idx < 2) { 817 printf("\nNCSI must runs on MAC#3 or MAC#4\n"); 818 return (finish_check(p_eng, Err_Flag_MACMode)); 819 } 820 #endif 821 } 822 823 p_eng->run.tdes_base = (uint32_t)(&tdes_buf[0]); 824 p_eng->run.rdes_base = (uint32_t)(&rdes_buf[0]); 825 826 if (p_eng->run.TM_IOTiming || p_eng->run.delay_margin) 827 p_eng->run.IO_MrgChk = 1; 828 else 829 p_eng->run.IO_MrgChk = 0; 830 831 p_eng->phy.Adr = p_eng->arg.phy_addr; 832 p_eng->phy.loopback = p_eng->arg.ctrl.b.phy_int_loopback; 833 p_eng->phy.default_phy = p_eng->run.TM_DefaultPHY; 834 835 p_eng->run.loop_max = p_eng->arg.loop_max; 836 calc_loop_check_num(p_eng); 837 838 //------------------------------------------------------------ 839 // Descriptor Number 840 //------------------------------------------------------------ 841 //------------------------------ 842 // [Dat]setup Des_Num 843 // [Dat]setup DMABuf_Size 844 // [Dat]setup DMABuf_Num 845 //------------------------------ 846 if (p_eng->arg.run_mode == MODE_DEDICATED) { 847 n_desp_min = p_eng->run.TM_IOTiming; 848 849 if (p_eng->arg.ctrl.b.phy_skip_check && 850 (p_eng->arg.test_mode == 0)) 851 /* for SMSC's LAN9303 issue */ 852 p_eng->dat.Des_Num = 114; 853 else { 854 switch (p_eng->arg.run_speed) { 855 case SET_1GBPS: 856 p_eng->dat.Des_Num = 857 p_eng->run.delay_margin 858 ? 100 859 : (n_desp_min) ? 512 : 4096; 860 break; 861 case SET_100MBPS: 862 p_eng->dat.Des_Num = 863 p_eng->run.delay_margin 864 ? 100 865 : (n_desp_min) ? 512 : 4096; 866 break; 867 case SET_10MBPS: 868 p_eng->dat.Des_Num = 869 p_eng->run.delay_margin 870 ? 100 871 : (n_desp_min) ? 100 : 830; 872 break; 873 case SET_1G_100M_10MBPS: 874 p_eng->dat.Des_Num = 875 p_eng->run.delay_margin 876 ? 100 877 : (n_desp_min) ? 100 : 830; 878 break; 879 case SET_100M_10MBPS: 880 p_eng->dat.Des_Num = 881 p_eng->run.delay_margin 882 ? 100 883 : (n_desp_min) ? 100 : 830; 884 break; 885 } 886 } 887 /* keep in order: Des_Num -> DMABuf_Size -> DMABuf_Num */ 888 p_eng->dat.Des_Num_Org = p_eng->dat.Des_Num; 889 p_eng->dat.DMABuf_Size = DMA_BufSize; 890 p_eng->dat.DMABuf_Num = DMA_BufNum; 891 892 if (DbgPrn_Info) { 893 printf("CheckBuf_MBSize : %d\n", 894 p_eng->run.CheckBuf_MBSize); 895 printf("LOOP_CheckNum : %d\n", 896 p_eng->run.LOOP_CheckNum); 897 printf("Des_Num : %d\n", p_eng->dat.Des_Num); 898 printf("DMA_BufSize : %d bytes\n", 899 p_eng->dat.DMABuf_Size); 900 printf("DMA_BufNum : %d\n", p_eng->dat.DMABuf_Num); 901 printf("DMA_PakSize : %d\n", DMA_PakSize); 902 printf("\n"); 903 } 904 if (2 > p_eng->dat.DMABuf_Num) 905 return (finish_check(p_eng, Err_Flag_DMABufNum)); 906 } 907 908 return 0; 909 } 910 911 /** 912 * @brief setup environment according to HW strap registers 913 */ 914 static uint32_t setup_interface(MAC_ENGINE *p_eng) 915 { 916 #ifdef CONFIG_ASPEED_AST2600 917 hw_strap1_t strap1; 918 hw_strap2_t strap2; 919 920 strap1.w = SCU_RD(0x500); 921 strap2.w = SCU_RD(0x510); 922 923 p_eng->env.is_1g_valid[0] = strap1.b.mac1_interface; 924 p_eng->env.is_1g_valid[1] = strap1.b.mac2_interface; 925 p_eng->env.is_1g_valid[2] = strap2.b.mac3_interface; 926 p_eng->env.is_1g_valid[3] = strap2.b.mac4_interface; 927 928 p_eng->env.at_least_1g_valid = 929 p_eng->env.is_1g_valid[0] | p_eng->env.is_1g_valid[1] | 930 p_eng->env.is_1g_valid[2] | p_eng->env.is_1g_valid[3]; 931 #else 932 hw_strap1_t strap1; 933 strap1.w = SCU_RD(0x70); 934 p_eng->env.is_1g_valid[0] = strap1.b.mac1_interface; 935 p_eng->env.is_1g_valid[1] = strap1.b.mac2_interface; 936 937 p_eng->env.at_least_1g_valid = 938 p_eng->env.is_1g_valid[0] | p_eng->env.is_1g_valid[1]; 939 #endif 940 return 0; 941 } 942 943 /** 944 * @brief setup chip compatibility accoriding to the chip ID register 945 */ 946 static uint32_t setup_chip_compatibility(MAC_ENGINE *p_eng) 947 { 948 uint32_t reg_addr; 949 uint32_t id, version; 950 uint32_t is_valid; 951 952 p_eng->env.ast2600 = 0; 953 p_eng->env.ast2500 = 0; 954 955 #if defined(CONFIG_ASPEED_AST2600) 956 reg_addr = 0x04; 957 #else 958 reg_addr = 0x7c; 959 #endif 960 is_valid = 0; 961 id = (SCU_RD(reg_addr) & GENMASK(31, 24)) >> 24; 962 version = (SCU_RD(reg_addr) & GENMASK(23, 16)) >> 16; 963 964 #if defined(CONFIG_FPGA_ASPEED) && defined(CONFIG_ASPEED_AST2600) 965 id = 0x5; 966 #endif 967 if (id == 0x5) { 968 printf("chip: AST2600 A%d\n", version); 969 p_eng->env.ast2600 = 1; 970 p_eng->env.ast2500 = 1; 971 p_eng->env.mac_num = 4; 972 p_eng->env.is_new_mdio_reg[0] = 1; 973 p_eng->env.is_new_mdio_reg[1] = 1; 974 p_eng->env.is_new_mdio_reg[2] = 1; 975 p_eng->env.is_new_mdio_reg[3] = 1; 976 is_valid = 1; 977 } else if (id == 0x4) { 978 printf("chip: AST2500 A%d\n", version); 979 p_eng->env.ast2500 = 1; 980 p_eng->env.mac_num = 2; 981 p_eng->env.is_new_mdio_reg[0] = MAC1_RD(0x40) >> 31; 982 p_eng->env.is_new_mdio_reg[1] = MAC2_RD(0x40) >> 31; 983 is_valid = 1; 984 } 985 986 if (0 == is_valid) { 987 printf("unknown chip\n"); 988 return 1; 989 } 990 991 return 0; 992 } 993 994 /** 995 * @brief setup environment accoriding to the HW strap and chip ID 996 */ 997 static uint32_t setup_env(MAC_ENGINE *p_eng) 998 { 999 if (0 != setup_chip_compatibility(p_eng)) { 1000 return 1; 1001 } 1002 1003 setup_interface(p_eng); 1004 return 0; 1005 } 1006 1007 static uint32_t init_mac_engine(MAC_ENGINE *p_eng, uint32_t mode) 1008 { 1009 memset(p_eng, 0, sizeof(MAC_ENGINE)); 1010 1011 if (0 != setup_env(p_eng)) { 1012 return 1; 1013 } 1014 1015 p_eng->arg.run_mode = mode; 1016 p_eng->arg.delay_scan_range = DEF_GIOTIMINGBUND; 1017 p_eng->arg.test_mode = DEF_GTESTMODE; 1018 1019 if (p_eng->arg.run_mode == MODE_NCSI ) { 1020 p_eng->arg.GARPNumCnt = DEF_GARPNUMCNT; 1021 p_eng->arg.GChannelTolNum = DEF_GCHANNEL2NUM; 1022 p_eng->arg.GPackageTolNum = DEF_GPACKAGE2NUM; 1023 p_eng->arg.ctrl.w = 0; 1024 p_eng->arg.run_speed = SET_100MBPS; // In NCSI mode, we set to 100M bps 1025 } else { 1026 p_eng->arg.user_def_val = DEF_GUSER_DEF_PACKET_VAL; 1027 p_eng->arg.phy_addr = DEF_GPHY_ADR; 1028 p_eng->arg.loop_inf = 0; 1029 p_eng->arg.loop_max = 0; 1030 p_eng->arg.ctrl.w = DEF_GCTRL; 1031 p_eng->arg.run_speed = DEF_GSPEED; 1032 } 1033 1034 p_eng->flg.print_en = 1; 1035 1036 p_eng->run.TM_TxDataEn = 1; 1037 p_eng->run.TM_RxDataEn = 1; 1038 p_eng->run.TM_NCSI_DiSChannel = 1; 1039 1040 /* setup 1041 * 1. delay control register 1042 * 2. driving strength control register and upper/lower bond 1043 * 3. MAC control register 1044 */ 1045 #ifdef CONFIG_ASPEED_AST2600 1046 p_eng->io.mac12_1g_delay.addr = SCU_BASE + 0x340; 1047 p_eng->io.mac12_1g_delay.tx_min = 0; 1048 p_eng->io.mac12_1g_delay.tx_max = 63; 1049 p_eng->io.mac12_1g_delay.rx_min = -63; 1050 p_eng->io.mac12_1g_delay.rx_max = 63; 1051 p_eng->io.mac12_1g_delay.rmii_tx_min = 0; 1052 p_eng->io.mac12_1g_delay.rmii_tx_max = 1; 1053 p_eng->io.mac12_1g_delay.rmii_rx_min = 0; 1054 p_eng->io.mac12_1g_delay.rmii_rx_max = 63; 1055 1056 p_eng->io.mac12_100m_delay.addr = SCU_BASE + 0x348; 1057 p_eng->io.mac12_100m_delay.tx_min = 0; 1058 p_eng->io.mac12_100m_delay.tx_max = 63; 1059 p_eng->io.mac12_100m_delay.rx_min = -63; 1060 p_eng->io.mac12_100m_delay.rx_max = 63; 1061 p_eng->io.mac12_10m_delay.addr = SCU_BASE + 0x34c; 1062 p_eng->io.mac12_10m_delay.tx_min = 0; 1063 p_eng->io.mac12_10m_delay.tx_max = 63; 1064 p_eng->io.mac12_10m_delay.rx_min = -63; 1065 p_eng->io.mac12_10m_delay.rx_max = 63; 1066 1067 p_eng->io.mac34_1g_delay.addr = SCU_BASE + 0x350; 1068 p_eng->io.mac34_1g_delay.tx_min = 0; 1069 p_eng->io.mac34_1g_delay.tx_max = 63; 1070 p_eng->io.mac34_1g_delay.rx_min = -63; 1071 p_eng->io.mac34_1g_delay.rx_max = 63; 1072 p_eng->io.mac34_1g_delay.rmii_tx_min = 0; 1073 p_eng->io.mac34_1g_delay.rmii_tx_max = 1; 1074 p_eng->io.mac34_1g_delay.rmii_rx_min = 0; 1075 p_eng->io.mac34_1g_delay.rmii_rx_max = 63; 1076 p_eng->io.mac34_100m_delay.addr = SCU_BASE + 0x358; 1077 p_eng->io.mac34_100m_delay.tx_min = 0; 1078 p_eng->io.mac34_100m_delay.tx_max = 63; 1079 p_eng->io.mac34_100m_delay.rx_min = -63; 1080 p_eng->io.mac34_100m_delay.rx_max = 63; 1081 p_eng->io.mac34_10m_delay.addr = SCU_BASE + 0x35c; 1082 p_eng->io.mac34_10m_delay.tx_min = 0; 1083 p_eng->io.mac34_10m_delay.tx_max = 63; 1084 p_eng->io.mac34_10m_delay.rx_min = -63; 1085 p_eng->io.mac34_10m_delay.rx_max = 63; 1086 1087 p_eng->io.mac34_drv_reg.addr = SCU_BASE + 0x458; 1088 p_eng->io.mac34_drv_reg.drv_max = 0x3; 1089 p_eng->io.drv_upper_bond = 0x3; 1090 p_eng->io.drv_lower_bond = 0; 1091 #else 1092 p_eng->io.mac12_1g_delay.addr = SCU_BASE + 0x48; 1093 p_eng->io.mac12_1g_delay.tx_min = 0; 1094 p_eng->io.mac12_1g_delay.tx_max = 63; 1095 p_eng->io.mac12_1g_delay.rx_min = 0; 1096 p_eng->io.mac12_1g_delay.rx_max = 63; 1097 p_eng->io.mac12_1g_delay.rmii_tx_min = 0; 1098 p_eng->io.mac12_1g_delay.rmii_tx_max = 1; 1099 p_eng->io.mac12_1g_delay.rmii_rx_min = 0; 1100 p_eng->io.mac12_1g_delay.rmii_rx_max = 63; 1101 p_eng->io.mac12_100m_delay.addr = SCU_BASE + 0xb8; 1102 p_eng->io.mac12_100m_delay.tx_min = 0; 1103 p_eng->io.mac12_100m_delay.tx_max = 63; 1104 p_eng->io.mac12_100m_delay.rx_min = 0; 1105 p_eng->io.mac12_100m_delay.rx_max = 63; 1106 p_eng->io.mac12_10m_delay.addr = SCU_BASE + 0xbc; 1107 p_eng->io.mac12_10m_delay.tx_min = 0; 1108 p_eng->io.mac12_10m_delay.tx_max = 63; 1109 p_eng->io.mac12_10m_delay.rx_min = 0; 1110 p_eng->io.mac12_10m_delay.rx_max = 63; 1111 1112 p_eng->io.mac34_1g_delay.addr = 0; 1113 p_eng->io.mac34_100m_delay.addr = 0; 1114 p_eng->io.mac34_10m_delay.addr = 0; 1115 1116 p_eng->io.mac12_drv_reg.addr = SCU_BASE + 0x90; 1117 p_eng->io.mac12_drv_reg.drv_max = 0x1; 1118 p_eng->io.drv_upper_bond = 0x1; 1119 p_eng->io.drv_lower_bond = 0; 1120 #endif 1121 return 0; 1122 } 1123 1124 static uint32_t parse_arg_dedicated(int argc, char *const argv[], 1125 MAC_ENGINE *p_eng) 1126 { 1127 switch (argc) { 1128 case 10: 1129 p_eng->arg.user_def_val = simple_strtol(argv[9], NULL, 16); 1130 case 9: 1131 p_eng->arg.delay_scan_range = simple_strtol(argv[8], NULL, 10); 1132 p_eng->arg.ieee_sel = p_eng->arg.delay_scan_range; 1133 case 8: 1134 p_eng->arg.phy_addr = simple_strtol(argv[7], NULL, 10); 1135 case 7: 1136 p_eng->arg.test_mode = simple_strtol(argv[6], NULL, 16); 1137 printf("test mode = %d\n", p_eng->arg.test_mode); 1138 case 6: 1139 p_eng->arg.loop_max = simple_strtol(argv[5], NULL, 10); 1140 if (p_eng->arg.loop_max == -1) { 1141 p_eng->arg.loop_inf = 1; 1142 } 1143 printf("loop max=%d, loop_inf=%d\n", p_eng->arg.loop_max, p_eng->arg.loop_inf); 1144 case 5: 1145 p_eng->arg.ctrl.w = simple_strtol(argv[4], NULL, 16); 1146 printf("ctrl=0x%05x\n", p_eng->arg.ctrl.w); 1147 case 4: 1148 p_eng->arg.run_speed = simple_strtol(argv[3], NULL, 16); 1149 printf("speed=0x%1x\n", p_eng->arg.run_speed); 1150 case 3: 1151 p_eng->arg.mdio_idx = simple_strtol(argv[2], NULL, 10); 1152 printf("mdio_idx=%d\n", p_eng->arg.mdio_idx); 1153 } 1154 1155 return 0; 1156 } 1157 1158 static uint32_t parse_arg_ncsi(int argc, char *const argv[], MAC_ENGINE *p_eng) 1159 { 1160 switch (argc) { 1161 case 8: 1162 p_eng->arg.GARPNumCnt = simple_strtol(argv[7], NULL, 10); 1163 case 7: 1164 p_eng->arg.ctrl.w = simple_strtol(argv[6], NULL, 16); 1165 printf("ctrl=0x%02x\n", p_eng->arg.ctrl.w); 1166 case 6: 1167 p_eng->arg.delay_scan_range = simple_strtol(argv[5], NULL, 10); 1168 case 5: 1169 p_eng->arg.test_mode = simple_strtol(argv[4], NULL, 16); 1170 case 4: 1171 p_eng->arg.GChannelTolNum = simple_strtol(argv[3], NULL, 10); 1172 case 3: 1173 p_eng->arg.GPackageTolNum = simple_strtol(argv[2], NULL, 10); 1174 } 1175 return 0; 1176 } 1177 1178 1179 static void disable_wdt(MAC_ENGINE *p_eng) 1180 { 1181 /* FIXME */ 1182 return; 1183 } 1184 1185 static uint32_t setup_data(MAC_ENGINE *p_eng) 1186 { 1187 if (p_eng->arg.run_mode == MODE_DEDICATED) { 1188 if (p_eng->run.tm_tx_only) 1189 setup_arp(p_eng); 1190 1191 p_eng->dat.FRAME_LEN = 1192 (uint32_t *)malloc(p_eng->dat.Des_Num * sizeof(uint32_t)); 1193 p_eng->dat.wp_lst = 1194 (uint32_t *)malloc(p_eng->dat.Des_Num * sizeof(uint32_t)); 1195 1196 if (!p_eng->dat.FRAME_LEN) 1197 return (finish_check(p_eng, Err_Flag_MALLOC_FrmSize)); 1198 if (!p_eng->dat.wp_lst) 1199 return (finish_check(p_eng, Err_Flag_MALLOC_LastWP)); 1200 1201 TestingSetup(p_eng); 1202 } else { 1203 if (p_eng->arg.GARPNumCnt != 0) 1204 setup_arp(p_eng); 1205 } 1206 1207 p_eng->run.speed_idx = 0; 1208 p_eng->io.drv_curr = mac_get_driving_strength(p_eng); 1209 if (mac_set_scan_boundary(p_eng)) 1210 return (finish_check(p_eng, 0)); 1211 1212 return 0; 1213 } 1214 1215 static uint32_t get_time_out_th(MAC_ENGINE *p_eng) 1216 { 1217 uint32_t time_out; 1218 1219 time_out = timeout_th_tbl[p_eng->run.speed_idx]; 1220 if (p_eng->run.TM_WaitStart) 1221 time_out = time_out * 10000; 1222 1223 return time_out; 1224 } 1225 uint32_t test_start(MAC_ENGINE *p_eng, PHY_ENGINE *p_phy_eng) 1226 { 1227 uint32_t drv, speed; 1228 int td, rd, tbegin, rbegin, tend, rend; 1229 int tstep, rstep; 1230 1231 uint32_t wrn_flag_allspeed = 0; 1232 uint32_t err_flag_allspeed = 0; 1233 uint32_t des_flag_allspeed = 0; 1234 uint32_t ncsi_flag_allspeed = 0; 1235 1236 memset(&p_eng->io.result_history[0][0], 0, 1237 sizeof(p_eng->io.result_history)); 1238 1239 for (speed = 0; speed < 3; speed++) { 1240 p_eng->flg.print_en = 1; 1241 p_eng->run.speed_idx = speed; 1242 mac_set_scan_boundary(p_eng); 1243 if (0 == p_eng->run.speed_sel[speed]) { 1244 continue; 1245 } 1246 1247 p_eng->run.timeout_th = get_time_out_th(p_eng); 1248 if (p_eng->arg.run_mode == MODE_DEDICATED) { 1249 if ((p_eng->arg.run_speed == SET_1G_100M_10MBPS) || 1250 (p_eng->arg.run_speed == SET_100M_10MBPS)) { 1251 if (p_eng->run.speed_sel[0]) 1252 p_eng->run.loop_max = 1253 p_eng->arg.loop_max; 1254 else if (p_eng->run.speed_sel[1]) 1255 p_eng->run.loop_max = 1256 p_eng->arg.loop_max / 100; 1257 else 1258 p_eng->run.loop_max = 1259 p_eng->arg.loop_max / 1000; 1260 1261 if (0 == p_eng->run.loop_max) 1262 p_eng->run.loop_max = 1; 1263 1264 calc_loop_check_num(p_eng); 1265 } 1266 //------------------------------ 1267 // PHY Initial 1268 //------------------------------ 1269 if (p_phy_eng->fp_set) { 1270 init_phy(p_eng, p_phy_eng); 1271 } 1272 1273 if (p_eng->flg.Err_Flag) 1274 return (finish_check(p_eng, 0)); 1275 } 1276 1277 //------------------------------ 1278 // [Start] The loop of different IO strength 1279 //------------------------------ 1280 debug("drirving scan range: %d ~ %d\n", 1281 p_eng->io.drv_lower_bond, p_eng->io.drv_upper_bond); 1282 for (drv = p_eng->io.drv_lower_bond; 1283 drv <= p_eng->io.drv_upper_bond; drv++) { 1284 if (p_eng->run.IO_MrgChk) { 1285 if (p_eng->run.TM_IOStrength) { 1286 mac_set_driving_strength(p_eng, drv); 1287 p_eng->io.drv_curr = mac_get_driving_strength(p_eng); 1288 } 1289 1290 if (p_eng->run.delay_margin) 1291 PrintIO_Header(p_eng, FP_LOG); 1292 if (p_eng->run.TM_IOTiming) 1293 PrintIO_Header(p_eng, FP_IO); 1294 PrintIO_Header(p_eng, STD_OUT); 1295 } else { 1296 if (p_eng->arg.run_mode == MODE_DEDICATED) { 1297 Print_Header(p_eng, STD_OUT); 1298 } 1299 } // End if (p_eng->run.IO_MrgChk) 1300 1301 //------------------------------ 1302 // [Start] The loop of different IO out delay 1303 //------------------------------ 1304 tbegin = p_eng->io.tx_delay_scan.begin; 1305 tend = p_eng->io.tx_delay_scan.end; 1306 tstep = p_eng->io.tx_delay_scan.step; 1307 1308 rbegin = p_eng->io.rx_delay_scan.begin; 1309 rend = p_eng->io.rx_delay_scan.end; 1310 rstep = p_eng->io.rx_delay_scan.step; 1311 1312 for (td = tbegin; td <= tend; td += tstep) { 1313 p_eng->io.Dly_out = td; 1314 p_eng->io.Dly_out_selval = td; 1315 if (p_eng->run.IO_MrgChk) { 1316 PrintIO_LineS(p_eng, STD_OUT); 1317 } // End if (p_eng->run.IO_MrgChk) 1318 1319 //------------------------------ 1320 // [Start] The loop of different IO in 1321 // delay 1322 //------------------------------ 1323 for (rd = rbegin; rd <= rend; rd += rstep) { 1324 p_eng->io.Dly_in = rd; 1325 if (p_eng->run.IO_MrgChk) { 1326 p_eng->io.Dly_in_selval = rd; 1327 scu_disable_mac(p_eng); 1328 mac_set_delay(p_eng, rd, td); 1329 scu_enable_mac(p_eng); 1330 } 1331 //------------------------------ 1332 // MAC Initial 1333 //------------------------------ 1334 init_mac(p_eng); 1335 if (p_eng->flg.Err_Flag) 1336 return (finish_check(p_eng, 0)); 1337 1338 if (p_eng->arg.run_mode == MODE_NCSI) { 1339 p_eng->io.result = 1340 phy_ncsi(p_eng); 1341 } else { 1342 p_eng->io.result = TestingLoop( 1343 p_eng, 1344 p_eng->run.LOOP_CheckNum); 1345 } 1346 1347 p_eng->io.result_history[rd + 64][td] |= 1348 p_eng->io.result; 1349 1350 /* Display to Log file and monitor */ 1351 if (p_eng->run.IO_MrgChk) { 1352 PrintIO_Line(p_eng, STD_OUT); 1353 1354 FPri_ErrFlag(p_eng, FP_LOG); 1355 1356 p_eng->flg.Wrn_Flag = 0; 1357 p_eng->flg.Err_Flag = 0; 1358 p_eng->flg.Des_Flag = 0; 1359 p_eng->flg.NCSI_Flag = 0; 1360 } 1361 } 1362 1363 if (p_eng->run.IO_MrgChk) { 1364 if (p_eng->run.TM_IOTiming) { 1365 PRINTF(FP_IO, "\n"); 1366 } 1367 printf("\n"); 1368 } 1369 } 1370 1371 if (!p_eng->run.tm_tx_only) 1372 FPri_ErrFlag(p_eng, FP_LOG); 1373 if (p_eng->run.TM_IOTiming) 1374 FPri_ErrFlag(p_eng, FP_IO); 1375 1376 FPri_ErrFlag(p_eng, STD_OUT); 1377 1378 wrn_flag_allspeed |= p_eng->flg.Wrn_Flag; 1379 err_flag_allspeed |= p_eng->flg.Err_Flag; 1380 des_flag_allspeed |= p_eng->flg.Err_Flag; 1381 ncsi_flag_allspeed |= p_eng->flg.Err_Flag; 1382 p_eng->flg.Wrn_Flag = 0; 1383 p_eng->flg.Err_Flag = 0; 1384 p_eng->flg.Des_Flag = 0; 1385 p_eng->flg.NCSI_Flag = 0; 1386 } 1387 1388 if (p_eng->arg.run_mode == MODE_DEDICATED) { 1389 if (p_phy_eng->fp_clr != 0) 1390 recov_phy(p_eng, p_phy_eng); 1391 } 1392 1393 p_eng->run.speed_sel[speed] = 0; 1394 p_eng->flg.print_en = 0; 1395 } // End for (speed = 0; speed < 3; speed++) 1396 1397 p_eng->flg.Wrn_Flag = wrn_flag_allspeed; 1398 p_eng->flg.Err_Flag = err_flag_allspeed; 1399 p_eng->flg.Des_Flag = des_flag_allspeed; 1400 p_eng->flg.NCSI_Flag = ncsi_flag_allspeed; 1401 1402 return (finish_check(p_eng, 0)); 1403 } 1404 1405 void dump_setting(MAC_ENGINE *p_eng) 1406 { 1407 /* dump env */ 1408 printf("===================\n"); 1409 printf("ast2600 compatible = %d\n", p_eng->env.ast2600); 1410 printf("ast2500 compatible = %d\n", p_eng->env.ast2500); 1411 printf("valid MAC number = %d\n", p_eng->env.mac_num); 1412 printf("use new MDIO register = %d %d %d %d\n", 1413 p_eng->env.is_new_mdio_reg[0], 1414 p_eng->env.is_new_mdio_reg[1], 1415 p_eng->env.is_new_mdio_reg[2], 1416 p_eng->env.is_new_mdio_reg[3]); 1417 printf("1G compatible = %d %d %d %d\n", 1418 p_eng->env.is_1g_valid[0], 1419 p_eng->env.is_1g_valid[1], 1420 p_eng->env.is_1g_valid[2], 1421 p_eng->env.is_1g_valid[3]); 1422 printf("===================\n"); 1423 1424 1425 } 1426 /** 1427 * @brief nettest main function 1428 */ 1429 int mac_test(int argc, char * const argv[], uint32_t mode) 1430 { 1431 MAC_ENGINE mac_eng; 1432 PHY_ENGINE phy_eng; 1433 1434 if (0 != init_mac_engine(&mac_eng, mode)) { 1435 printf("init MAC engine fail\n"); 1436 return 1; 1437 } 1438 1439 if (argc <= 1) { 1440 print_usage(&mac_eng); 1441 return 1; 1442 } 1443 1444 mac_eng.arg.mac_idx = simple_strtol(argv[1], NULL, 16); 1445 1446 /* default mdio_idx = mac_idx */ 1447 mac_eng.arg.mdio_idx = mac_eng.arg.mac_idx; 1448 if (MODE_DEDICATED == mode) 1449 parse_arg_dedicated(argc, argv, &mac_eng); 1450 else 1451 parse_arg_ncsi(argc, argv, &mac_eng); 1452 1453 setup_running(&mac_eng); 1454 1455 dump_setting(&mac_eng); 1456 1457 /* init PHY engine */ 1458 phy_eng.fp_set = NULL; 1459 phy_eng.fp_clr = NULL; 1460 1461 if (mac_eng.arg.ctrl.b.rmii_50m_out && 0 == mac_eng.run.is_rgmii ) { 1462 mac_set_rmii_50m_output_enable(&mac_eng); 1463 } 1464 1465 push_reg(&mac_eng); 1466 disable_wdt(&mac_eng); 1467 1468 mac_set_addr(&mac_eng); 1469 if (mac_eng.arg.ctrl.b.mac_int_loopback) 1470 mac_set_interal_loopback(&mac_eng); 1471 1472 scu_set_pinmux(&mac_eng); 1473 1474 scu_disable_mac(&mac_eng); 1475 scu_enable_mac(&mac_eng); 1476 if (mac_eng.arg.run_mode == MODE_DEDICATED) { 1477 if (1 == phy_find_addr(&mac_eng)) { 1478 phy_sel(&mac_eng, &phy_eng); 1479 } 1480 } 1481 1482 /* Data Initial */ 1483 setup_data(&mac_eng); 1484 1485 mac_eng.flg.all_fail = 1; 1486 mac_eng.io.init_done = 1; 1487 for(int i = 0; i < 3; i++) 1488 mac_eng.run.speed_sel[i] = mac_eng.run.speed_cfg[i]; 1489 1490 //------------------------------ 1491 // [Start] The loop of different speed 1492 //------------------------------ 1493 print_legend(); 1494 test_start(&mac_eng, &phy_eng); 1495 1496 return 0; 1497 } 1498