1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <exports.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <reset.h> 12 #include <fdtdec.h> 13 #include <asm/io.h> 14 15 #include "dptest.h" 16 17 /* Version info*/ 18 #define MAINVER 0 19 #define SUBVER 3 20 #define TEMPVER 2 21 22 #define YEAR 2022 23 #define MONTH 07 24 #define DAY 11 25 26 /* Compile define */ 27 /* #define RE_DRIVER */ 28 /* #define INTERNAL */ 29 30 /* Debug define */ 31 #define DBG_Print 32 33 #define DBG_ERR 0x00000001 /* DBG_ERROR */ 34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */ 35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */ 36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */ 37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */ 38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */ 39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */ 40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */ 41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */ 42 /* #define DBG_AUX_W 0x00002000 *//*DBG_AUX_W_VALUE */ 43 44 int DBG_LEVEL = 0x00000040; /* Information and stage */ 45 /* int DBG_LEVEL = 0x0000107F; *//*Fully */ 46 /* int DBG_LEVEL = 0x00000001; *//*Error */ 47 48 #ifdef DBG_Print 49 #define DBG(Level, format, args...) if ((Level) & DBG_LEVEL) printf(format, ##args) 50 #else 51 #define DBG(Level, format, args...) 52 #endif 53 54 int PHY_Cfg_N; 55 int PHY_Cfg; 56 int PHY_Cfg_1; 57 int TX_SSCG_Cfg; 58 int DP_Rate; 59 int Deemphasis_Level; 60 int Deemphasis_Level_1; 61 int Deemphasis_Show; 62 int Deemphasis_RD; 63 int Swing_Level; 64 int SSCG; 65 int SSC_SHIFT; 66 int Current_Item; 67 int GFlag; 68 uchar EDID[256]; 69 70 int I2C_PORT;/* I2c port */ 71 int I2C_BASE; 72 int I2C_BUFF; 73 uchar RD_VAL; 74 75 /* Record DP Sink status */ 76 uchar bEn_Frame; 77 uchar Link_Aux_RD_Val; 78 uchar CR_EQ_Keep; 79 int Deemlevel[3] = {DP_DEEMP_2, DP_DEEMP_0, DP_DEEMP_1}; 80 uchar Auto_Link_Rate; 81 uchar Auto_Lane_Count; 82 /* uchar Patch_Normal_Behavior; */ 83 84 static int 85 do_ast_dptest(cmd_tbl_t *cmdtp, int flags, int argc, char *const argv[]) 86 { 87 char received = 0; 88 char execute_test = 0; 89 int flag = 0, i; 90 char *Temp = NULL; 91 92 /* Default setting */ 93 DP_Rate = DP_RATE_1_62; 94 95 Deemphasis_Show = DP_DEEMP_0; 96 Deemphasis_Level = DP_DEEMP_0; 97 Deemphasis_Level_1 = DP_DEEMP_2; 98 Swing_Level = 2; 99 SSCG = DP_SSCG_ON; 100 SSC_SHIFT = 1; 101 102 /* Obtain the argc / argv */ 103 for (i = 1; i < argc; i++) { 104 if (argv[i][0] == '-') { 105 switch (argv[i][1]) { 106 case 'D': 107 case 'd': 108 Temp = (char *)&argv[i][2]; 109 DBG_LEVEL = (int)(strtoul(Temp, NULL, 16)); 110 DBG_LEVEL |= DBG_ERR; /* Add must print. */ 111 printf("DBG_LEVEL change into 0x%x\n", DBG_LEVEL); 112 break; 113 case 'R': 114 case 'r': 115 Temp = (char *)&argv[i][2]; 116 I2C_PORT = (int)(strtoul(Temp, NULL, 16)); 117 printf("I2C_PORT change into 0x%x\n", I2C_PORT); 118 break; 119 default: 120 I2C_PORT = 0x0; 121 break; 122 } 123 } 124 } 125 126 printf("ASPEED DP Physical Layer Test Tool V %d.%d.%d\n", MAINVER, SUBVER, TEMPVER); 127 #ifdef INTERNAL 128 printf("Internal Version\n"); 129 #endif 130 131 printf("Build Date: %d.%d.%d\n\n", YEAR, MONTH, DAY); 132 133 printf("PLEASE REFER USER MANUAL BEFORE TEST!!\n\n"); 134 135 /* DP TX MCU reset */ 136 DPTX_MCU_Reset(); 137 printf("DP TX MCU Initial Done!\n"); 138 139 /* DP phy set */ 140 DPPHY_Set(); 141 printf("DP Physcial Config Done!\n"); 142 143 printf("Commands as below:\n"); 144 printf("0: Change SSC on/off\n"); 145 printf("1: Set data rate 1.62\n"); 146 printf("2: Set data rate 2.7\n"); 147 #ifdef INTERNAL 148 printf("3: DE_LVL = 1, DE_LVL_1 = 2\n"); 149 printf("4: DE_LVL = 0, DE_LVL_1 = 0\n"); 150 printf("5: DE_LVL = 2, DE_LVL_1 = 1\n"); 151 #endif 152 printf("!: Show configs\n\n"); 153 154 printf("TestItems as below:\n"); 155 printf("x: auto test\n"); 156 printf("a: PRBS7\n"); 157 printf("Press ESC key to leave test ...\n\n"); 158 159 // While for auto testing 160 while (1) { 161 if (tstc()) { 162 received = getc(); 163 164 /* printf("Press %d\n",received); */ 165 166 /* Set parameters path */ 167 if (received >= '1' && received <= '9') { 168 switch (received) { 169 /* Press "1" : Set DP_Rate as 1.62 */ 170 case '1': 171 DP_Rate = DP_RATE_1_62; 172 PRINT_RATE_1_62; 173 break; 174 /* Press "2" : Set DP_Rate as 2.701 */ 175 case '2': 176 DP_Rate = DP_RATE_2_70; 177 PRINT_RATE_2_70; 178 break; 179 /* Press "3" : Set DP_Rate as 5.40 */ 180 /* case '3': */ 181 /* DP_Rate = DP_RATE_5_40; */ 182 /* PRINT_RATE_5_40 */ 183 /* break; */ 184 #ifdef INTERNAL 185 /* Press "3" : Set Deemphasis_Level as 1 / Deemphasis_Level_1 as 2 */ 186 case '3': 187 Deemphasis_Level = DP_DEEMP_1; 188 Deemphasis_Level_1 = DP_DEEMP_2; 189 Deemphasis_Show = DP_DEEMP_0; 190 Deemphasis_RD = Deemphasis_Show; 191 PRINT_DEEMP_0; 192 break; 193 /* Press "4" : Set Deemphasis_Level as 0 / Deemphasis_Level_1 as 0 */ 194 case '4': 195 Deemphasis_Level = DP_DEEMP_0; 196 Deemphasis_Level_1 = DP_DEEMP_0; 197 Deemphasis_Show = DP_DEEMP_1; 198 Deemphasis_RD = Deemphasis_Show; 199 PRINT_DEEMP_1; 200 break; 201 /* Press "5" : Set Deemphasis_Level as 2 / Deemphasis_Level_1 as 1 */ 202 case '5': 203 Deemphasis_Level = DP_DEEMP_2; 204 Deemphasis_Level_1 = DP_DEEMP_1; 205 Deemphasis_Show = DP_DEEMP_2; 206 Deemphasis_RD = Deemphasis_Show; 207 PRINT_DEEMP_2; 208 break; 209 #endif 210 case '6': 211 SSC_SHIFT = 2; 212 break; 213 case '7': 214 SSC_SHIFT = 3; 215 break; 216 default: 217 break; 218 } 219 220 if (execute_test) 221 printf("The parameter is applied next measure!\n"); 222 223 } else if (received == '!') /* show config */ { 224 if (execute_test) 225 printf("Measurement is executed!\n"); 226 else 227 printf("Measurement is stopped!\n"); 228 229 DPPHYTX_Show_Cfg(); 230 } else if (received == '0') /* change sscfg */ { 231 if (SSCG == DP_SSCG_ON) { 232 SSCG = DP_SSCG_OFF; 233 PRINT_SSCG_OFF; 234 } else { 235 SSCG = DP_SSCG_ON; 236 PRINT_SSCG_ON; 237 } 238 239 /* SSCG could be applied without reset device. */ 240 if (execute_test) { 241 printf("Apply SSCG into current measurement !\n\n"); 242 TX_SSCG_Cfg = DP_TX_RDY_TEST; 243 /* TX_SSCG_Cfg |= SSCG; */ 244 TX_SSCG_Cfg |= DP_SSCG_ON; 245 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 246 } 247 } else { 248 /* Check the ESC key */ 249 if (received == 27) { 250 execute_test = 0; 251 DPTX_MCU_Reset(); 252 printf("'ESC' is pressed!\n"); 253 break; 254 } 255 256 /* If the test is execute, reset it */ 257 if (execute_test) { 258 execute_test = 0; 259 DPTX_MCU_Reset(); 260 261 printf("Stop current measurement !\n\n\n\n\n\n"); 262 } 263 264 /* Clear flag */ 265 flag = 0; 266 267 Current_Item = received; 268 269 switch (received) { 270 case 'a': 271 flag = (F_EMPHASIS_NULL | F_PAT_PRBS7); 272 break; 273 #ifdef INTERNAL 274 case 'b': 275 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 276 break; 277 278 case 'c': 279 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT); 280 break; 281 282 case 'd': /* Non-Transition Voltage Range Measurement - PLTPAT */ 283 flag = (F_EMPHASIS | F_PAT_PLTPAT); 284 break; 285 286 case 'e': /* Pre-Emphasis Level Test and Pre-Emphasis Level Delta Test- PRBS7 */ 287 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 288 break; 289 290 case 'f': /* Non-Transition Voltage Range Measurement - PRBS7 */ 291 flag = (F_EMPHASIS | F_PAT_PRBS7); 292 break; 293 294 case 'g': /* Total - PRBS7 */ 295 flag = (F_EMPHASIS_1 | F_PAT_D10_2); 296 break; 297 298 case 'h': 299 printf("Change the Swing value from request\n"); 300 flag = (F_EMPHASIS_1 | F_PAT_PRBS7 | F_SHOW_SWING); 301 break; 302 303 case 'i': 304 printf("Change the Swing value from request\n"); 305 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT | DP_TX_HIGH_SPEED | F_SHOW_SWING); 306 break; 307 308 case 'j': 309 flag = F_PAT_AUX; 310 break; 311 #endif 312 case 'x': /* Auto hand shaking with DPR-100 */ 313 flag = F_EXE_AUTO; 314 break; 315 316 default: 317 printf("Non - define command!\n"); 318 break; 319 } 320 321 // Execute testing 322 if (flag) { 323 execute_test = 1; 324 GFlag = flag; 325 326 if (flag & F_PAT_AUX) { 327 printf("######################################\n"); 328 printf("#Current DP TX setting is shown below#\n"); 329 printf("######################################\n\n"); 330 331 DPPHYTX_Show_Item(Current_Item); 332 Apply_AUX_Mesument(flag); 333 } else if (flag & F_EXE_AUTO) { 334 printf("#########################\n"); 335 printf("#Enter DP TX Auto Test!!#\n"); 336 printf("#########################\n\n"); 337 338 Apply_Auto_Preset(0x1); 339 Apply_Auto_Mesument(); 340 Apply_Auto_Preset(0x0); 341 342 printf("#########################\n"); 343 printf("#Leave DP TX Auto Test!!#\n"); 344 printf("#########################\n\n"); 345 } else { 346 DPPHYTX_Show_Cfg(); 347 Apply_Main_Mesument(flag); 348 } 349 } 350 } 351 } 352 mdelay(200); 353 }; 354 355 printf("\n\n"); 356 return 0; 357 } 358 359 /* Temp for cording here */ 360 void Apply_Auto_Preset(char Init) 361 { 362 /* Fill some nessary register value for auto test */ 363 if (Init) { 364 /* Enable MCU received interrupt */ 365 writel(0x00e80000, DP_TX_INT_CLEAR); 366 367 /* Set HPD irq time interval */ 368 writel(0x04e300fb, DP_TX_IRQ_CFG); 369 370 /* Set HPD event time interval */ 371 writel(0x000007d1, DP_TX_EVENT_CFG); 372 } else { 373 /* Recover */ 374 writel(0x0, DP_TX_INT_CLEAR); 375 writel(0x0, DP_TX_IRQ_CFG); 376 writel(0x0, DP_TX_EVENT_CFG); 377 } 378 } 379 380 /* READ EDID */ 381 void Read_EDID_128(char Offset) 382 { 383 char AUX_Data[16] = {0}; 384 uchar Length = 1; 385 uchar Status = 0; 386 uchar i, j; 387 388 DBG(DBG_A_EDID, "R EDID Offset %d\n", Offset); 389 390 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 391 392 AUX_Data[0] = Offset; 393 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 394 395 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 396 397 Length = 16; 398 399 // Read 128 bytes block 400 for (i = 0; i < 8; i++) { 401 do { 402 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 403 DBG(DBG_A_EDID, "EDID read %d!\n", i); 404 405 udelay(100); 406 } while (Status == 0x20); 407 408 /* copy from temp into EDID */ 409 for (j = 0; j < 16; j++) 410 EDID[Offset + i * 16 + j] = AUX_Data[j]; 411 } 412 413 Length = 1; 414 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 415 } 416 417 void Apply_EDID_Reading(void) 418 { 419 char AUX_Data[16] = {0}; 420 uchar Length = 1; 421 uchar Status = 0; 422 423 DBG(DBG_STAGE, "Apply EDID Reading!\n"); 424 425 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 426 427 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 428 429 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 430 431 /* Check read EDID header */ 432 Length = 4; 433 do { 434 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 435 436 udelay(100); 437 } while (Status == 0x20); 438 439 DBG(DBG_A_EDID, "EDID First 4 is 0x%X_0x%X_0x%X_0x%X\n", AUX_Data[0], AUX_Data[1], AUX_Data[2], AUX_Data[3]); 440 441 Length = 1; 442 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 443 444 DBG(DBG_A_EDID, "Read 128!\n"); 445 Read_EDID_128(0x0); 446 447 /* If the extension bit is set, then read back next block */ 448 if (EDID[0x7E] == 0x1) { 449 DBG(DBG_A_EDID, "Read 256!\n"); 450 Read_EDID_128(0x80); 451 } 452 } 453 454 /* LINK TRAIN */ 455 uchar Adjust_CR_EQ_Train(int TrainPat, uchar ADJStatus) 456 { 457 char AUX_Data[16] = {0}; 458 uchar Ret = 0; 459 uchar Length = 1; 460 uchar Status = 0; 461 uchar AUX_R_Level = 0; 462 uchar AUX_W_Level = 0; 463 uchar DE_Level = 0x0; 464 uchar CR_Status = 0; 465 int value = 0; 466 uchar bFirst = 1; 467 uchar tempkeep = 0; 468 469 /* Set the main link pattern with TPS1 / TPS2 for Lanex_CR_Done */ 470 value = ((readl(DP_TX_MAIN_PAT) & ~(0x30000000)) | TrainPat); 471 writel(value, DP_TX_MAIN_PAT); 472 DBG(DBG_A_SUB, "1.A_C_E Set Link Pattern\n"); 473 474 /* AST phy 0xE4 Bit28 (0x1000000) / DP 0x102 Bit0 : TPS1 */ 475 /* AST phy 0xE4 Bit29 (0x2000000) / DP 0x102 Bit1 : TPS2 */ 476 if (TrainPat == 0x10000000) 477 AUX_Data[0] = 0x21; 478 else 479 AUX_Data[0] = 0x22; 480 481 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 482 DBG(DBG_A_SUB, "2.A_C_E W 0x102 set 0x%x\n", AUX_Data[0]); 483 484 /* First */ 485 if (bFirst) { 486 Length = 4; 487 488 AUX_Data[0] = CR_EQ_Keep; 489 AUX_Data[1] = CR_EQ_Keep; 490 AUX_Data[2] = CR_EQ_Keep; 491 AUX_Data[3] = CR_EQ_Keep; 492 tempkeep = CR_EQ_Keep; 493 494 do { 495 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 496 DBG(DBG_A_SUB, "3.A_C_E W 0x103 - 0x106 set\n"); 497 } while (Status == 0x20); 498 499 Length = 6; 500 501 udelay(1200); 502 503 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 504 DBG(DBG_A_SUB, "4.A_C_E R 0x200 - 0x205 read back\n"); 505 506 if ((AUX_Data[2] & ADJStatus) == ADJStatus) { 507 CR_EQ_Keep = tempkeep; 508 return Ret; 509 } 510 511 bFirst = 0; 512 } 513 514 /* loop for CR_lock */ 515 do { 516 Length = 1; 517 518 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 519 DBG(DBG_A_SUB, "5.A_C_E R 0x206 read back\n"); 520 AUX_R_Level = AUX_Data[0]; 521 522 AUX_R(AUX_CMD_R, 0x207, (int *)(&AUX_Data), &Length, &Status); 523 DBG(DBG_A_SUB, "6.A_C_E R 0x207 read back\n"); 524 525 /* Update SW Level */ 526 switch (AUX_R_Level & 0x33) { 527 case 0x00: 528 AUX_W_Level = 00; 529 break; 530 case 0x11: 531 AUX_W_Level = 01; 532 break; 533 default: 534 AUX_W_Level = 06; 535 break; 536 } 537 538 /* Update SW Level */ 539 switch (AUX_R_Level & 0xCC) { 540 case 0x00: 541 /* AUX_W_Level |= 00; */ 542 DE_Level = 0; 543 break; 544 case 0x44: 545 AUX_W_Level |= 0x08; 546 DE_Level = 1; 547 break; 548 default: 549 AUX_W_Level |= 0x30; 550 DE_Level = 2; 551 break; 552 } 553 554 /* Set the de-emphsis value */ 555 value = ((readl(DP_TX_PHY_CFG) & ~(0x33000000)) | Deemlevel[DE_Level]); 556 writel(value, DP_TX_PHY_CFG); 557 DBG(DBG_A_SUB, "6.A_C_E Set Phy config %d\n", DE_Level); 558 559 DBG(DBG_A_SUB, "Link AUX_W_Level is 0x%x\n", AUX_W_Level); 560 561 Length = 4; 562 563 AUX_Data[0] = AUX_W_Level; 564 AUX_Data[1] = AUX_W_Level; 565 AUX_Data[2] = AUX_W_Level; 566 AUX_Data[3] = AUX_W_Level; 567 tempkeep = AUX_W_Level; 568 569 do { 570 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 571 DBG(DBG_A_SUB, "7.A_C_E W 0x103 - 0x106 set\n"); 572 } while (Status == 0x20); 573 574 udelay(1380); 575 576 Length = 6; 577 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 578 DBG(DBG_A_SUB, "8.A_C_E R 0x200 - 0x205 read back\n"); 579 580 CR_Status = AUX_Data[2] & ADJStatus; 581 582 /* Decrease speed because the deemphasis level reach max value */ 583 if (AUX_W_Level == 0x36) { 584 Ret = 1; 585 break; 586 } 587 588 } while (CR_Status != ADJStatus); 589 590 CR_EQ_Keep = tempkeep; 591 592 return Ret; 593 } 594 595 uchar Link_Train_Flow(char Link_Level) 596 { 597 char AUX_Data[16] = {0}; 598 uchar Length = 1; 599 uchar Status = 0; 600 uchar Ret = 0; 601 int value = 0; 602 603 DBG(DBG_STAGE, "Link train flow! Level : %d\n", Link_Level); 604 605 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 606 DBG(DBG_A_SUB, "1.Link R 0x101 read back\n"); 607 608 /* Normal / Test case */ 609 if (Auto_Lane_Count) 610 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 611 else 612 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 613 614 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 615 DBG(DBG_A_SUB, "2.Link W 0x101 clear\n"); 616 617 /* Set different clock bit rate */ 618 value = ((readl(DP_TX_MAIN_SET) & ~(0x300)) | (Link_Level << 8)); 619 writel(value, DP_TX_MAIN_SET); 620 621 switch (Link_Level) { 622 case 0x1: /* 2.7 */ 623 AUX_Data[0] = 0x0a; 624 break; 625 626 default: /* 1.62 */ 627 AUX_Data[0] = 0x06; 628 break; 629 } 630 631 AUX_W(AUX_CMD_W, 0x100, (int *)(&AUX_Data), &Length, &Status); 632 DBG(DBG_A_SUB, "3.Link W 0x100 set\n"); 633 634 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 635 DBG(DBG_A_SUB, "4.Link R 0x101 read back\n"); 636 637 /* Normal / Test case */ 638 if (Auto_Lane_Count) 639 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 640 else 641 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 642 643 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 644 DBG(DBG_A_SUB, "5.Link W 0x101 clear\n"); 645 646 /* Set the 2 lanes and enhance frame by checking AUX 0x2 bit 7 */ 647 value = ((readl(DP_TX_MAIN_SET) & ~(0x1070)) | 0x20); 648 649 if (bEn_Frame) 650 value |= 0x1000; 651 652 writel(value, DP_TX_MAIN_SET); 653 654 value = ((readl(DP_TX_PHY_CFG) & ~(0x3000)) | 0x3000); 655 656 writel(value, DP_TX_PHY_CFG); 657 658 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 659 DBG(DBG_A_SUB, "6.Link R 0x101 read back\n"); 660 661 /* Normal / Test case */ 662 if (Auto_Lane_Count) 663 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 664 else 665 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 666 667 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 668 DBG(DBG_A_SUB, "7.Link W 0x101 clear\n"); 669 670 /* Set the main link control on */ 671 value = ((readl(DP_TX_PHY_SET) & ~(0x100)) | 0x100); 672 673 udelay(1000); 674 udelay(1500); 675 676 writel(value, DP_TX_PHY_SET); 677 678 do { 679 value = (readl(DP_TX_PHY_SET) & 0x200); 680 } while (value != 0x200); 681 DBG(DBG_A_SUB, "8.Link Main Link Ready\n"); 682 683 /* Adjust for CR */ 684 if (Adjust_CR_EQ_Train(0x10000000, 0x11)) { 685 Ret = 1; 686 return Ret; 687 } 688 689 /* Adjust for EQ */ 690 if (Adjust_CR_EQ_Train(0x20000000, 0x77)) { 691 Ret = 1; 692 return Ret; 693 } 694 695 return Ret; 696 } 697 698 void Apply_HPD_Normal(void) 699 { 700 char AUX_Data[16] = {0}; 701 uchar Length = 1; 702 uchar Status = 0; 703 int value = 0; 704 705 DBG(DBG_STAGE, "HPD Normal set!\n"); 706 707 AUX_Data[0] = 0x01; 708 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 709 DBG(DBG_NOR, "1.HPD_N W 0x600 set power!\n"); 710 711 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 712 DBG(DBG_NOR, "2.HPD_N R 0x0 read back is 0x%X!\n", AUX_Data[0]); 713 714 Length = 8; 715 AUX_R(AUX_CMD_R, 0x500, (int *)(&AUX_Data), &Length, &Status); 716 DBG(DBG_NOR, "3.HPD_N R 0x500 - 0x508 read back\n"); 717 718 Length = 14; 719 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 720 DBG(DBG_NOR, "4.HPD_N R 0x0 - 0xD read back\n"); 721 722 bEn_Frame = AUX_Data[2] & 0x80; 723 Link_Aux_RD_Val = AUX_Data[14]; 724 725 if (bEn_Frame) 726 DBG(DBG_NOR, "4.HPD_N R 0x2 En_Frame_Cap\n"); 727 728 Length = 1; 729 AUX_R(AUX_CMD_R, 0xe, (int *)(&AUX_Data), &Length, &Status); 730 DBG(DBG_NOR, "5.HPD_N R 0xE read back\n"); 731 732 /* Read EDID */ 733 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Enter\n"); 734 735 Apply_EDID_Reading(); 736 737 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Leave\n"); 738 739 Length = 2; 740 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 741 DBG(DBG_NOR, "7.HPD_N R 0x200 - 0x201 read back.\n"); 742 743 Length = 1; 744 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 745 DBG(DBG_NOR, "8.HPD_N R 0x68028 read back.\n"); 746 747 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 748 DBG(DBG_NOR, "9.HPD_N R 0x68028 read back.\n"); 749 750 AUX_R(AUX_CMD_R, 0x600, (int *)(&AUX_Data), &Length, &Status); 751 DBG(DBG_NOR, "10.HPD_N R 0x600 read back.\n"); 752 753 AUX_Data[0] = 0x01; 754 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 755 DBG(DBG_NOR, "11.HPD_N W 0x600 set power!\n"); 756 757 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Enter\n"); 758 759 Status = Link_Train_Flow(0x1); 760 761 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Leave\n"); 762 763 if (Status) { 764 AUX_Data[0] = 0x20; 765 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 766 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x1 Fail!!\n"); 767 768 DBG(DBG_NOR, "13.HPD_N Link_Train_Flow 0x0 Enter\n"); 769 770 Status = Link_Train_Flow(0x0); 771 772 DBG(DBG_NOR, "13.HPD_NLink_Train_Flow 0x0 Leave\n"); 773 774 if (Status) { 775 AUX_Data[0] = 0x20; 776 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 777 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x0 Fail!!\n"); 778 779 DBG(DBG_ERR, "### CAUTION!! LINK TRAN FAIL!! ###\n"); 780 781 return; 782 } 783 } 784 785 /* Link successful */ 786 AUX_Data[0] = 0x00; 787 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 788 DBG(DBG_NOR, "14.HPD_N W 0x102 clear!\n"); 789 790 /* Fill idle pattern */ 791 value = ((readl(DP_TX_MAIN_PAT) & ~(0x31000000)) | 0x01000000); 792 writel(value, DP_TX_MAIN_PAT); 793 DBG(DBG_NOR, "15.HPD_N Fill idle pattern!\n"); 794 795 Length = 1; 796 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 797 DBG(DBG_NOR, "16.HPD_N R 0x68028 read back.\n"); 798 799 Length = 5; 800 AUX_R(AUX_CMD_R, 0x68000, (int *)(&AUX_Data), &Length, &Status); 801 DBG(DBG_NOR, "17.HPD_N R 0x68000 - 0x68004 read back.\n"); 802 803 Length = 1; 804 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 805 DBG(DBG_NOR, "18.HPD_N R 0x68028 read back.\n"); 806 807 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 808 DBG(DBG_NOR, "19.HPD_N R 0x68028 read back.\n"); 809 810 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 811 DBG(DBG_NOR, "20.HPD_N R 0x0 read back.\n"); 812 } 813 814 void Apply_HPD_Auto_Test(void) 815 { 816 char AUX_Data[16]; 817 uchar Length = 0; 818 uchar Status = 0; 819 uchar clear_auto_test = 0; 820 uchar auto_test_link = 0; 821 uchar auto_test_phy = 0; 822 uchar swing0 = 0, preemphasis0 = 0; 823 uchar swing1 = 0, preemphasis1 = 0; 824 int flag = 0; 825 char temp0 = 0, temp1 = 0; 826 char temp206 = 0; 827 828 DBG(DBG_STAGE, "HPD Auto test set!\n"); 829 830 /* Set power D0 */ 831 AUX_Data[0] = 0x01; 832 Length = 1; 833 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 834 DBG(DBG_A_TEST, "1.HP_I W 0x600 done!\n"); 835 836 Length = 6; 837 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 838 DBG(DBG_A_TEST, "2.HP_I R 0x200 - 0x206 done!\n"); 839 840 Length = 1; 841 AUX_R(AUX_CMD_R, 0x201, (int *)(&AUX_Data), &Length, &Status); 842 DBG(DBG_A_TEST, "3.HP_I R 0x201 : 0x%x\n", AUX_Data[0]); 843 844 /* Obtain auto test */ 845 if (AUX_Data[0] & 0x2) 846 clear_auto_test = 1; 847 else 848 clear_auto_test = 0; 849 850 /* Read dummy */ 851 Length = 3; 852 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 853 Length = 1; 854 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 855 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 856 Length = 3; 857 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 858 Length = 1; 859 AUX_R(AUX_CMD_R, 0x205, (int *)(&AUX_Data), &Length, &Status); 860 DBG(DBG_A_TEST, "4. HP_I R Dummy!\n"); 861 862 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 863 DBG(DBG_A_TEST, "5. HP_I Link Rate R 0x219 : 0x%x\n", AUX_Data[0]); 864 865 if (AUX_Data[0] == 0x06) { 866 Auto_Link_Rate = AUX_Data[0]; 867 DP_Rate = DP_RATE_1_62; 868 PRINT_RATE_1_62; 869 } else if (AUX_Data[0] == 0x0a) { 870 Auto_Link_Rate = AUX_Data[0]; 871 DP_Rate = DP_RATE_2_70; 872 PRINT_RATE_2_70; 873 } else if (AUX_Data[0] == 0x14) { 874 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 875 return; 876 } 877 878 if (clear_auto_test) { 879 AUX_Data[0] = 0x02; 880 AUX_W(AUX_CMD_W, 0x201, (int *)(&AUX_Data), &Length, &Status); 881 DBG(DBG_A_TEST, "1.HP_I CA W 0x201 clear auto!\n"); 882 clear_auto_test = 0; 883 884 /* Fetch Testing data */ 885 AUX_R(AUX_CMD_R, 0x218, (int *)(&AUX_Data), &Length, &Status); 886 DBG(DBG_A_TEST, "2.HP_I CA R 0x218 : 0x%x\n", AUX_Data[0]); 887 888 /* Check auto test link flag */ 889 if (AUX_Data[0] & 0x1) 890 auto_test_link = 1; 891 else 892 auto_test_link = 0; 893 894 /* Check auto test phy flag */ 895 if (AUX_Data[0] & 0x8) 896 auto_test_phy = 1; 897 else 898 auto_test_phy = 0; 899 DBG(DBG_A_TEST, "auto test link(%d) phy(%d)\n", auto_test_link, auto_test_phy); 900 901 if (auto_test_link) { 902 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 903 DBG(DBG_A_TEST, "1.HP_I TL R 0x219 : 0x%x\n", AUX_Data[0]); 904 905 if (AUX_Data[0] == 0x06) { 906 Auto_Link_Rate = AUX_Data[0]; 907 DP_Rate = DP_RATE_1_62; 908 PRINT_RATE_1_62; 909 } else if (AUX_Data[0] == 0x0a) { 910 Auto_Link_Rate = AUX_Data[0]; 911 DP_Rate = DP_RATE_2_70; 912 PRINT_RATE_2_70; 913 } else if (AUX_Data[0] == 0x14) { 914 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 915 return; 916 } 917 918 AUX_R(AUX_CMD_R, 0x220, (int *)(&AUX_Data), &Length, &Status); 919 DBG(DBG_A_TEST, "2.HP_I TL R 0x220 : 0x%x\n", AUX_Data[0]); 920 Auto_Lane_Count = AUX_Data[0] & 0x1F; 921 922 AUX_Data[0] = 0x01; 923 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 924 DBG(DBG_A_TEST, "3.HP_I TL W 0x260 test ACK\n"); 925 926 mdelay(95); 927 928 /* Set power D0 */ 929 AUX_Data[0] = 0x01; 930 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 931 DBG(DBG_A_TEST, "3.1 HP_I W 0x600 done!\n"); 932 933 switch (Auto_Link_Rate) { 934 case 0x06: 935 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Enter\n"); 936 Status = Link_Train_Flow(0x0); 937 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Leave\n"); 938 break; 939 940 case 0x0a: 941 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Enter\n"); 942 Status = Link_Train_Flow(0x1); 943 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Leave\n"); 944 break; 945 946 default: 947 DBG(DBG_ERR, "!!BAD LINK RATE!!\n"); 948 return; 949 } 950 951 if (Status) { 952 DBG(DBG_ERR, "!!AUTO TEST LINK FAIL!!\n"); 953 return; 954 } 955 956 /* Link successful */ 957 AUX_Data[0] = 0x00; 958 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 959 DBG(DBG_A_TEST, "5.HP_I TL Link clear!\n"); 960 961 auto_test_link = 0; 962 } 963 964 if (auto_test_phy) { 965 Length = 1; 966 flag = 0; 967 temp206 = 0; 968 969 AUX_R(AUX_CMD_R, 0x248, (int *)(&AUX_Data), &Length, &Status); 970 DBG(DBG_A_TEST, "1.HP_I TP R 0x248 : 0x%x!\n", AUX_Data[0]); 971 972 if (AUX_Data[0] == 0x01) { 973 flag |= F_PAT_D10_2; 974 DBG(DBG_A_TEST, "HP_I TP D10.2!\n"); 975 } else if (AUX_Data[0] == 0x03) { 976 flag |= F_PAT_PRBS7; 977 DBG(DBG_A_TEST, "HP_I TP PRBS7!\n"); 978 } 979 980 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 981 DBG(DBG_A_TEST, "2.HP_I TP R 0x206 : 0x%x!\n", AUX_Data[0]); 982 983 /* Temp for verified */ 984 DBG(DBG_INF, "Read value 0x206 : 0x%x!\n", AUX_Data[0]); 985 986 /* Check Swing */ 987 temp0 = (AUX_Data[0] & 0x03); 988 temp1 = (AUX_Data[0] & 0x30); 989 990 /* Check Swing0 */ 991 switch (temp0) { 992 case 0x2: 993 swing0 = 0x2; 994 temp206 |= 6; 995 break; 996 case 0x1: 997 swing0 = 0x1; 998 temp206 |= 1; 999 break; 1000 case 0x0: 1001 swing0 = 0x0; 1002 break; 1003 default: 1004 DBG(DBG_ERR, "HP_I TP 0x206 other swing0 val %x!\n", temp0); 1005 break; 1006 } 1007 1008 /* Check Swing1 */ 1009 switch (temp1) { 1010 case 0x20: 1011 swing1 = 0x2; 1012 temp206 |= 6; 1013 break; 1014 case 0x10: 1015 swing1 = 0x1; 1016 temp206 |= 1; 1017 break; 1018 case 0x00: 1019 swing1 = 0x0; 1020 break; 1021 default: 1022 DBG(DBG_ERR, "HP_I TP 0x206 other swing1 val %x!\n", temp1); 1023 break; 1024 } 1025 1026 if (swing0 != swing1) 1027 DBG(DBG_ERR, "Swing 0 / 1 diff val %x!\n", AUX_Data[0]); 1028 1029 /* Check Pre-emphasis */ 1030 temp0 = (AUX_Data[0] & 0x0C); 1031 temp1 = (AUX_Data[0] & 0xC0); 1032 1033 /* Check Pre-emphasis0 */ 1034 switch (temp0) { 1035 case 0x8: 1036 preemphasis0 = 0x2; 1037 temp206 |= 0x30; 1038 break; 1039 case 0x4: 1040 preemphasis0 = 0x1; 1041 temp206 |= 0x08; 1042 break; 1043 case 0x0: 1044 preemphasis0 = 0x0; 1045 break; 1046 default: 1047 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis0 val %x!\n", temp0); 1048 break; 1049 } 1050 1051 /* Check Pre-emphasis1 */ 1052 switch (temp1) { 1053 case 0x80: 1054 preemphasis1 = 0x2; 1055 temp206 |= 0x30; 1056 break; 1057 case 0x40: 1058 preemphasis1 = 0x1; 1059 temp206 |= 0x08; 1060 break; 1061 case 0x00: 1062 preemphasis1 = 0x0; 1063 break; 1064 default: 1065 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis1 val %x!\n", temp1); 1066 break; 1067 } 1068 1069 if (preemphasis0 != preemphasis1) 1070 DBG(DBG_ERR, "Preemphasis 0 / 1 diff val %x!\n", AUX_Data[0]); 1071 1072 /* Judgement */ 1073 if (swing0 == 0x2 || swing1 == 0x2) 1074 Swing_Level = 0x2; 1075 else if (swing0 == 1 || swing1 == 0x1) 1076 Swing_Level = 0x1; 1077 else if (swing0 == 0x0 || swing1 == 0x0) 1078 Swing_Level = 0x0; 1079 1080 if (preemphasis0 == 0x2 || preemphasis1 == 0x2) { 1081 Deemphasis_RD = DP_DEEMP_2; 1082 Deemphasis_Level_1 = DP_DEEMP_1; 1083 DBG(DBG_ERR, "!!De-type 1 P_2 !!\n"); 1084 } else if (preemphasis0 == 0x1 || preemphasis1 == 0x1) { 1085 Deemphasis_RD = DP_DEEMP_1; 1086 Deemphasis_Level_1 = DP_DEEMP_0; 1087 DBG(DBG_ERR, "!!De-type 0 P_1 !!\n"); 1088 } else if (preemphasis0 == 0x0 || preemphasis1 == 0x0) { 1089 Deemphasis_RD = DP_DEEMP_0; 1090 Deemphasis_Level_1 = DP_DEEMP_2; 1091 DBG(DBG_ERR, "!!De-type 2 P_0 !!\n"); 1092 } 1093 1094 DBG(DBG_INF, "!!Swing %d / Pre-emphasis %d !!\n", swing0, preemphasis0); 1095 1096 flag |= F_EMPHASIS_1; 1097 1098 AUX_R(AUX_CMD_R, 0x102, (int *)(&AUX_Data), &Length, &Status); 1099 DBG(DBG_A_TEST, "3.HP_I TP R 0x102 : 0x%x\n", AUX_Data[0]); 1100 temp0 = AUX_Data[0]; 1101 1102 Length = 2; 1103 AUX_R(AUX_CMD_R, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1104 DBG(DBG_A_TEST, "4.HP_I TP R 0x10b : 0x%x\n", AUX_Data[0]); 1105 1106 AUX_W(AUX_CMD_W, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1107 DBG(DBG_A_TEST, "5.HP_I TP W 0x10b done!\n"); 1108 1109 AUX_Data[0] = temp0 | 0x20; 1110 Length = 1; 1111 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 1112 DBG(DBG_A_TEST, "6.HP_I TP W 0x102 done!\n"); 1113 1114 AUX_Data[0] = temp206; 1115 AUX_Data[1] = temp206; 1116 Length = 2; 1117 1118 do { 1119 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 1120 DBG(DBG_A_TEST, "7.HP_I TP W 0x103 - 0x104 done!\n"); 1121 } while (Status == 0x20); 1122 1123 DPPHYTX_Show_Cfg(); 1124 Apply_Main_Mesument(flag); 1125 1126 Length = 1; 1127 AUX_Data[0] = 0x01; 1128 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 1129 DBG(DBG_A_TEST, "8.HP_I TP W 0x260 done!\n"); 1130 1131 DBG(DBG_STAGE, "Leave Apply Auto Test\n"); 1132 1133 auto_test_phy = 0; 1134 } 1135 clear_auto_test = 0; 1136 } 1137 } 1138 1139 /* TEST SECTION */ 1140 void Apply_Auto_Mesument(void) 1141 { 1142 char auto_received = 0; 1143 int temp = 0, wdata = 0; 1144 int breakcount = 0; 1145 1146 while (1) { 1147 breakcount = 0; 1148 1149 /* Wait HPD */ 1150 do { 1151 temp = (readl(DP_TX_INT_STATUS) & 0x3800); 1152 breakcount++; 1153 1154 if (breakcount == 0x96000) { 1155 /* A simple break for esc press received */ 1156 break; 1157 } 1158 1159 } while (!(temp & 0x3800)); 1160 1161 if (temp) { 1162 /* Clear AUX write interrupt status */ 1163 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1164 writel(wdata, DP_TX_INT_CLEAR); 1165 } 1166 1167 /* Interrupt occur */ 1168 if (temp & 0x2800) { 1169 /* Initial global parameter */ 1170 Auto_Link_Rate = 0; 1171 Auto_Lane_Count = 0; 1172 bEn_Frame = 0; 1173 CR_EQ_Keep = 0; 1174 1175 if (temp & 0x2000) { 1176 printf("DP HPD irq is detected!\n"); 1177 Apply_HPD_Normal(); 1178 } 1179 1180 if (temp & 0x800) { 1181 printf("DP HPD event is detected!\n"); 1182 Apply_HPD_Auto_Test(); 1183 } 1184 } 1185 1186 /* Leave auto test if the 'ESC' is pressed */ 1187 if (tstc()) { 1188 auto_received = getc(); 1189 1190 /* Check the ESC key */ 1191 if (auto_received == 27) { 1192 printf("'ESC' is pressed under auto test!\n\n"); 1193 return; 1194 } 1195 1196 printf("DP TX auto test is executed!\n"); 1197 } 1198 } 1199 } 1200 1201 void Apply_Main_Mesument(int flag) 1202 { 1203 DPTX_MCU_Reset(); 1204 1205 /* Emphasis setting */ 1206 if (flag & F_EMPHASIS_NULL) 1207 writel(PHY_Cfg_N, DP_TX_PHY_CFG); 1208 else if (flag & F_EMPHASIS) 1209 writel(PHY_Cfg, DP_TX_PHY_CFG); 1210 else if (flag & F_EMPHASIS_1) 1211 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1212 1213 if (flag & F_RES_HIGH) 1214 writel(DP_TX_HIGH_SPEED, DP_TX_RES_CFG); 1215 else 1216 writel(DP_TX_NOR_SPEED, DP_TX_RES_CFG); 1217 1218 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1219 1220 DPPHY_Set(); 1221 1222 if (flag & F_PAT_PRBS7) 1223 Set_PRBS7(); 1224 else if (flag & F_PAT_PLTPAT) 1225 Set_PLTPAT(); 1226 else if (flag & F_PAT_HBR2CPAT) 1227 Set_HBR2CPAT(); 1228 else if (flag & F_PAT_D10_2) 1229 Set_D10_1(); 1230 1231 /* ssc special patch */ 1232 if (flag & F_PAT_D10_2) { 1233 /*Apply special patch*/ 1234 writel(SSC_SHIFT << 10, DP_TX_RES_CFG); 1235 TX_SSCG_Cfg |= DP_SSCG_ON; 1236 } else { 1237 /*Recover into original setting*/ 1238 writel(0x00000000, DP_TX_RES_CFG); 1239 } 1240 1241 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 1242 } 1243 1244 void Apply_AUX_Mesument(int flag) 1245 { 1246 DPTX_MCU_Reset(); 1247 DPPHY_Set(); 1248 1249 writel(0x0F000000, DP_AUX_ADDR_LEN); 1250 writel(0x80000010, DP_AUX_REQ_CFG); 1251 } 1252 1253 /* FUNCTION SECTION */ 1254 /* i2c set */ 1255 #ifdef RE_DRIVER 1256 void Set_Redriver(void) 1257 { 1258 int value = 0x0; 1259 uchar offset = 0x0; 1260 uchar *set_table = &set_table0; 1261 1262 if (Deemphasis_RD == DP_DEEMP_1) 1263 set_table = &set_table1; 1264 else if (Deemphasis_RD == DP_DEEMP_2) 1265 set_table = &set_table2; 1266 1267 RD_VAL = set_table[Swing_Level]; 1268 1269 printf("RD_VAL is 0x%x\n", RD_VAL); 1270 1271 writel(0x600, I2C_BASE + I2C0_COUNT_O); 1272 value = (0x0000f0f0 | (RD_VAL << 24)); 1273 writel(value, I2C_BUFF); 1274 printf("value0 is 0x%x\n", value); 1275 value = (RD_VAL | (RD_VAL << 8) | (RD_VAL << 16) | (RD_VAL << 24)); 1276 writel(value, (I2C_BUFF + 0x4)); 1277 printf("value1 is 0x%x\n", value); 1278 writel(0x70010063, (I2C_BASE + I2C0_EXECUTE_O)); 1279 mdelay(1000); 1280 } 1281 1282 /* i2c single initial */ 1283 void I2C_L_Initial(void) 1284 { 1285 I2C_BASE = (I2C0_BASE + (I2C_DEV_OFFSET * I2C_PORT)); 1286 I2C_BUFF = (I2C0_BUFF + (I2C_BUFF_OFFSET * I2C_PORT)); 1287 1288 writel(0x0, I2C_BASE); 1289 mdelay(1); 1290 writel(0x28001, I2C_BASE); 1291 writel(0x344001, I2C_BASE + I2C0_TIMMING_O); 1292 writel(0xFFFFFFFF, I2C_BASE + I2C0_INT_STATUS_O); 1293 writel(0x0, I2C_BASE + I2C0_INT_O); 1294 mdelay(10); 1295 } 1296 1297 /* i2c golbal iniitial */ 1298 void I2C_G_Initial(void) 1299 { 1300 /* i2c multi-function */ 1301 writel(0x0FFF3000, MP_SCU410); 1302 writel(0x0F00FF00, MP_SCU414); 1303 writel(0xCFFF001F, MP_SCU418); 1304 writel(0xF00000FF, MP_SCU4b0); 1305 writel(0xF0FF00FF, MP_SCU4b4); 1306 writel(0x0000FF00, MP_SCU4b8); 1307 1308 /* I2c control */ 1309 writel(0x16, (I2C_GBASE + 0xC)); 1310 writel(0x041230C6, (I2C_GBASE + 0x10)); 1311 1312 mdelay(1000); 1313 } 1314 #endif 1315 1316 void DPTX_MCU_Reset(void) 1317 { 1318 /* Reset DPMCU & Release DPTX */ 1319 writel(0x20000000, SYS_REST); 1320 writel(0x10000000, SYS_REST_CLR); 1321 1322 /* Wait for apply setting */ 1323 mdelay(1000); 1324 } 1325 1326 void DPPHY_Set(void) 1327 { 1328 int value = 0, count = 0; 1329 1330 /* Clear power on reset */ 1331 writel(0x10000000, DP_TX_PHY_SET); 1332 mdelay(1); 1333 1334 /* Clear DPTX reset */ 1335 writel(0x11000000, DP_TX_PHY_SET); 1336 mdelay(1); 1337 1338 /* Turn on Main link / Aux channel */ 1339 writel(0x11001100, DP_TX_PHY_SET); 1340 mdelay(1); 1341 1342 while (value != DP_TX_RDY_TEST) { 1343 value = readl(DP_TX_PHY_SET); 1344 mdelay(1); 1345 count++; 1346 } 1347 } 1348 1349 char DPPHYTX_Show_Cfg(void) 1350 { 1351 char SetFail = 0; 1352 1353 PHY_Cfg = DP_PHY_INIT_CFG; 1354 PHY_Cfg_1 = DP_PHY_INIT_CFG; 1355 TX_SSCG_Cfg = DP_TX_RDY_TEST; 1356 1357 /* Show the setting */ 1358 1359 printf("######################################\n"); 1360 printf("#Current DP TX setting is shown below#\n"); 1361 printf("######################################\n\n"); 1362 1363 DPPHYTX_Show_Item(Current_Item); 1364 1365 switch (DP_Rate) { 1366 case DP_RATE_1_62: 1367 PRINT_RATE_1_62; 1368 break; 1369 1370 case DP_RATE_2_70: 1371 PRINT_RATE_2_70; 1372 break; 1373 1374 case DP_RATE_5_40: 1375 PRINT_RATE_5_40; 1376 break; 1377 1378 default: 1379 PRINT_INVALID; 1380 printf("DP Rate\n"); 1381 SetFail = 1; 1382 break; 1383 } 1384 1385 switch (Deemphasis_Show) { 1386 case DP_DEEMP_0: 1387 if (GFlag & F_SHOW_SWING) 1388 PRINT_SWING_0; 1389 else 1390 PRINT_EMPVAL_0; 1391 break; 1392 1393 case DP_DEEMP_1: 1394 if (GFlag & F_SHOW_SWING) 1395 PRINT_SWING_1; 1396 else 1397 PRINT_EMPVAL_1; 1398 break; 1399 1400 case DP_DEEMP_2: 1401 if (GFlag & F_SHOW_SWING) 1402 PRINT_SWING_2; 1403 else 1404 PRINT_EMPVAL_2; 1405 break; 1406 1407 default: 1408 PRINT_INVALID; 1409 printf("Deemphasis Level\n"); 1410 SetFail = 1; 1411 break; 1412 } 1413 1414 switch (Swing_Level) { 1415 case 0: 1416 PRINT_SWING_0; 1417 break; 1418 1419 case 1: 1420 PRINT_SWING_1; 1421 break; 1422 1423 case 2: 1424 PRINT_SWING_2; 1425 break; 1426 1427 default: 1428 PRINT_INVALID; 1429 printf("Swing Level\n"); 1430 SetFail = 1; 1431 break; 1432 } 1433 1434 PHY_Cfg = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level); 1435 PHY_Cfg_1 = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level_1); 1436 PHY_Cfg_N = DP_PHY_INIT_CFG | (DP_Rate | DP_DEEMP_2); 1437 1438 switch (SSCG) { 1439 case DP_SSCG_ON: 1440 /*PRINT_SSCG_ON;*/ 1441 break; 1442 1443 case DP_SSCG_OFF: 1444 /*PRINT_SSCG_OFF;*/ 1445 break; 1446 1447 default: 1448 PRINT_INVALID; 1449 printf("SSCG\n"); 1450 SetFail = 1; 1451 break; 1452 } 1453 /* TX_SSCG_Cfg |= SSCG; */ 1454 TX_SSCG_Cfg |= DP_SSCG_ON; 1455 1456 printf("\n"); 1457 1458 return SetFail; 1459 } 1460 1461 void DPPHYTX_Show_Item(char received) 1462 { 1463 switch (received) { 1464 case 'a': 1465 PRINT_ITEM_A; 1466 break; 1467 1468 case 'b': 1469 PRINT_ITEM_B; 1470 break; 1471 1472 case 'c': 1473 PRINT_ITEM_C; 1474 break; 1475 1476 case 'd': 1477 PRINT_ITEM_D; 1478 break; 1479 1480 case 'e': 1481 PRINT_ITEM_E; 1482 break; 1483 1484 case 'f': 1485 PRINT_ITEM_F; 1486 break; 1487 1488 case 'g': 1489 PRINT_ITEM_G; 1490 break; 1491 1492 case 'h': 1493 PRINT_ITEM_H; 1494 break; 1495 1496 case 'i': 1497 PRINT_ITEM_I; 1498 break; 1499 1500 case 'j': 1501 PRINT_ITEM_J; 1502 break; 1503 1504 case 'x': 1505 PRINT_ITEM_X; 1506 break; 1507 1508 default: 1509 break; 1510 } 1511 1512 printf("\n"); 1513 } 1514 1515 void Set_PRBS7(void) 1516 { 1517 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1518 writel((DP_PY_PAT | DP_PY_PAT_PRB7), DP_TX_PHY_PAT); 1519 } 1520 1521 void Set_HBR2CPAT(void) 1522 { 1523 int value = 0, count = 0; 1524 1525 writel(DP_TX_MAIN_ADV, DP_TX_MAIN_SET); 1526 1527 writel(DP_TX_PAT_HBR2, DP_TX_MAIN_PAT); 1528 writel((DP_PY_PAT | DP_PY_PAT_SCRB), DP_TX_PHY_PAT); 1529 1530 writel(DP_TX_MAIN_TRA, DP_TX_MAIN_CFG); 1531 mdelay(1); 1532 1533 while (value != DP_TX_RDY_25201) { 1534 value = (readl(DP_TX_MAIN_CFG) & 0xFFF); 1535 mdelay(1); 1536 count++; 1537 } 1538 1539 /* Reset for signal apply */ 1540 writel((DP_TX_MAIN_ADV | DP_TX_PY_RESET), DP_TX_MAIN_SET); 1541 } 1542 1543 void Set_PLTPAT(void) 1544 { 1545 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1546 1547 writel(DP_TX_PLTPAT_0, DP_TX_CUS_PAT_0); 1548 writel(DP_TX_PLTPAT_1, DP_TX_CUS_PAT_1); 1549 writel(DP_TX_PLTPAT_2, DP_TX_CUS_PAT_2); 1550 1551 writel((DP_PY_PAT | DP_PY_PAT_CUS), DP_TX_PHY_PAT); 1552 } 1553 1554 void Set_D10_1(void) 1555 { 1556 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1557 1558 writel(DP_TX_PAT_TPS1, DP_TX_MAIN_PAT); 1559 writel(DP_PY_PAT, DP_TX_PHY_PAT); 1560 } 1561 1562 uchar AUX_R(int aux_cmd, int aux_addr, int *aux_r_data, uchar *length, uchar *status) 1563 { 1564 int wdata = 0, temp = 0; 1565 uchar len = *length; 1566 1567 /* Check valid length */ 1568 if (len >= 1) 1569 len -= 1; 1570 else 1571 return 1; 1572 1573 /* Prepare AUX write address and data */ 1574 wdata = (int)((len << 24) | aux_addr); 1575 writel(wdata, DP_AUX_ADDR_LEN); 1576 1577 DBG(DBG_AUX_R, "AUX Read on 0x%x with %d bytes.\n", aux_addr, *length); 1578 1579 /* Fire AUX read */ 1580 writel(aux_cmd, DP_AUX_REQ_CFG); 1581 1582 /* Wait AUX read finish or timeout */ 1583 do { 1584 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1585 } while (!(temp & 0xC000)); 1586 1587 /* Clear AUX write interrupt status */ 1588 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1589 writel(wdata, DP_TX_INT_CLEAR); 1590 1591 if (temp & AUX_CMD_DONE) { 1592 /* Read back data count */ 1593 *aux_r_data = readl(DP_AUX_R_D_0); 1594 1595 DBG(DBG_AUX_R, "Data on 0x0 is 0x%x.\n", *aux_r_data); 1596 1597 if ((*length) > 0x4) { 1598 aux_r_data++; 1599 *aux_r_data = readl(DP_AUX_R_D_4); 1600 DBG(DBG_AUX_R, "Data on 0x4 is 0x%x.\n", *aux_r_data); 1601 } 1602 1603 if ((*length) > 0x8) { 1604 aux_r_data++; 1605 *aux_r_data = readl(DP_AUX_R_D_8); 1606 DBG(DBG_AUX_R, "Data on 0x8 is 0x%x.\n", *aux_r_data); 1607 } 1608 1609 if ((*length) > 0xC) { 1610 aux_r_data++; 1611 *aux_r_data = readl(DP_AUX_R_D_C); 1612 DBG(DBG_AUX_R, "Data on 0xC is 0x%x.\n", *aux_r_data); 1613 } 1614 1615 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1616 return 0; 1617 } else { 1618 return 1; 1619 } 1620 } 1621 1622 uchar AUX_W(int aux_cmd, int aux_addr, int *aux_w_data, uchar *length, uchar *status) 1623 { 1624 int wdata = 0, temp = 0; 1625 uchar len = *length; 1626 1627 /* Check valid length */ 1628 if (len >= 1) 1629 len -= 1; 1630 else 1631 return 1; 1632 1633 /* Prepare AUX write address and data */ 1634 wdata = (int)((len << 24) | aux_addr); 1635 writel(wdata, DP_AUX_ADDR_LEN); 1636 1637 writel(*aux_w_data, DP_AUX_W_D_0); 1638 1639 if ((*length) > 0x4) { 1640 aux_w_data++; 1641 writel(*aux_w_data, DP_AUX_W_D_4); 1642 } 1643 1644 if ((*length) > 0x8) { 1645 aux_w_data++; 1646 writel(*aux_w_data, DP_AUX_W_D_8); 1647 } 1648 1649 if ((*length) > 0xC) { 1650 aux_w_data++; 1651 writel(*aux_w_data, DP_AUX_W_D_C); 1652 } 1653 1654 /* Fire AUX write */ 1655 writel(aux_cmd, DP_AUX_REQ_CFG); 1656 1657 /* Wait AUX write finish or timeout */ 1658 do { 1659 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1660 } while (!(temp & 0xC000)); 1661 1662 /* Clear AUX write interrupt status */ 1663 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1664 writel(wdata, DP_TX_INT_CLEAR); 1665 1666 if (temp & AUX_CMD_DONE) { 1667 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1668 return 0; 1669 } else { 1670 return 1; 1671 } 1672 } 1673 1674 U_BOOT_CMD(dptest, 2, 0, do_ast_dptest, "ASPEED Display Port phy test", "ASPEED DP test v.0.2.9"); 1675