1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) ASPEED Technology Inc. 4 */ 5 6 #include <common.h> 7 #include <exports.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <errno.h> 11 #include <reset.h> 12 #include <fdtdec.h> 13 #include <asm/io.h> 14 15 #include "dptest.h" 16 17 /* Version info*/ 18 #define MAINVER 0 19 #define SUBVER 3 20 #define TEMPVER 2 21 22 #define YEAR 2022 23 #define MONTH 07 24 #define DAY 11 25 26 /* Compile define */ 27 /* #define RE_DRIVER */ 28 /* #define INTERNAL */ 29 30 /* Debug define */ 31 #define DBG_Print 32 33 #define DBG_ERR 0x00000001 /* DBG_ERROR */ 34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */ 35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */ 36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */ 37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */ 38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */ 39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */ 40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */ 41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */ 42 /* #define DBG_AUX_W 0x00002000 *//*DBG_AUX_W_VALUE */ 43 44 int DBG_LEVEL = 0x00000040; /* Information and stage */ 45 /* int DBG_LEVEL = 0x0000107F; *//*Fully */ 46 /* int DBG_LEVEL = 0x00000001; *//*Error */ 47 48 #ifdef DBG_Print 49 #define DBG(Level, format, args...) if ((Level) & DBG_LEVEL) printf(format, ##args) 50 #else 51 #define DBG(Level, format, args...) 52 #endif 53 54 int PHY_Cfg_N; 55 int PHY_Cfg; 56 int PHY_Cfg_1; 57 int TX_SSCG_Cfg; 58 int DP_Rate; 59 int Deemphasis_Level; 60 int Deemphasis_Level_1; 61 int Deemphasis_Show; 62 int Deemphasis_RD; 63 int Swing_Level; 64 int SSCG; 65 int Current_Item; 66 int GFlag; 67 uchar EDID[256]; 68 69 int I2C_PORT;/* I2c port */ 70 int I2C_BASE; 71 int I2C_BUFF; 72 uchar RD_VAL; 73 74 /* Record DP Sink status */ 75 uchar bEn_Frame; 76 uchar Link_Aux_RD_Val; 77 uchar CR_EQ_Keep; 78 int Deemlevel[3] = {DP_DEEMP_2, DP_DEEMP_0, DP_DEEMP_1}; 79 uchar Auto_Link_Rate; 80 uchar Auto_Lane_Count; 81 /* uchar Patch_Normal_Behavior; */ 82 83 static int 84 do_ast_dptest(cmd_tbl_t *cmdtp, int flags, int argc, char *const argv[]) 85 { 86 char received = 0; 87 char execute_test = 0; 88 int flag = 0, i; 89 char *Temp = NULL; 90 91 /* Default setting */ 92 DP_Rate = DP_RATE_1_62; 93 94 Deemphasis_Show = DP_DEEMP_0; 95 Deemphasis_Level = DP_DEEMP_0; 96 Deemphasis_Level_1 = DP_DEEMP_2; 97 Swing_Level = 2; 98 SSCG = DP_SSCG_ON; 99 100 /* Obtain the argc / argv */ 101 for (i = 1; i < argc; i++) { 102 if (argv[i][0] == '-') { 103 switch (argv[i][1]) { 104 case 'D': 105 case 'd': 106 Temp = (char *)&argv[i][2]; 107 DBG_LEVEL = (int)(strtoul(Temp, NULL, 16)); 108 DBG_LEVEL |= DBG_ERR; /* Add must print. */ 109 printf("DBG_LEVEL change into 0x%x\n", DBG_LEVEL); 110 break; 111 case 'R': 112 case 'r': 113 Temp = (char *)&argv[i][2]; 114 I2C_PORT = (int)(strtoul(Temp, NULL, 16)); 115 printf("I2C_PORT change into 0x%x\n", I2C_PORT); 116 break; 117 default: 118 I2C_PORT = 0x0; 119 break; 120 } 121 } 122 } 123 124 printf("ASPEED DP Physical Layer Test Tool V %d.%d.%d\n", MAINVER, SUBVER, TEMPVER); 125 #ifdef INTERNAL 126 printf("Internal Version\n"); 127 #endif 128 129 printf("Build Date: %d.%d.%d\n\n", YEAR, MONTH, DAY); 130 131 printf("PLEASE REFER USER MANUAL BEFORE TEST!!\n\n"); 132 133 /* DP TX MCU reset */ 134 DPTX_MCU_Reset(); 135 printf("DP TX MCU Initial Done!\n"); 136 137 /* DP phy set */ 138 DPPHY_Set(); 139 printf("DP Physcial Config Done!\n"); 140 141 printf("Commands as below:\n"); 142 printf("0: Change SSC on/off\n"); 143 printf("1: Set data rate 1.62\n"); 144 printf("2: Set data rate 2.7\n"); 145 #ifdef INTERNAL 146 printf("3: DE_LVL = 1, DE_LVL_1 = 2\n"); 147 printf("4: DE_LVL = 0, DE_LVL_1 = 0\n"); 148 printf("5: DE_LVL = 2, DE_LVL_1 = 1\n"); 149 #endif 150 printf("!: Show configs\n\n"); 151 152 printf("TestItems as below:\n"); 153 printf("x: auto test\n"); 154 printf("a: PRBS7\n"); 155 printf("Press ESC key to leave test ...\n\n"); 156 157 // While for auto testing 158 while (1) { 159 if (tstc()) { 160 received = getc(); 161 162 /* printf("Press %d\n",received); */ 163 164 /* Set parameters path */ 165 if (received >= '1' && received <= '9') { 166 switch (received) { 167 /* Press "1" : Set DP_Rate as 1.62 */ 168 case '1': 169 DP_Rate = DP_RATE_1_62; 170 PRINT_RATE_1_62; 171 break; 172 /* Press "2" : Set DP_Rate as 2.701 */ 173 case '2': 174 DP_Rate = DP_RATE_2_70; 175 PRINT_RATE_2_70; 176 break; 177 /* Press "3" : Set DP_Rate as 5.40 */ 178 /* case '3': */ 179 /* DP_Rate = DP_RATE_5_40; */ 180 /* PRINT_RATE_5_40 */ 181 /* break; */ 182 #ifdef INTERNAL 183 /* Press "3" : Set Deemphasis_Level as 1 / Deemphasis_Level_1 as 2 */ 184 case '3': 185 Deemphasis_Level = DP_DEEMP_1; 186 Deemphasis_Level_1 = DP_DEEMP_2; 187 Deemphasis_Show = DP_DEEMP_0; 188 Deemphasis_RD = Deemphasis_Show; 189 PRINT_DEEMP_0; 190 break; 191 /* Press "4" : Set Deemphasis_Level as 0 / Deemphasis_Level_1 as 0 */ 192 case '4': 193 Deemphasis_Level = DP_DEEMP_0; 194 Deemphasis_Level_1 = DP_DEEMP_0; 195 Deemphasis_Show = DP_DEEMP_1; 196 Deemphasis_RD = Deemphasis_Show; 197 PRINT_DEEMP_1; 198 break; 199 /* Press "5" : Set Deemphasis_Level as 2 / Deemphasis_Level_1 as 1 */ 200 case '5': 201 Deemphasis_Level = DP_DEEMP_2; 202 Deemphasis_Level_1 = DP_DEEMP_1; 203 Deemphasis_Show = DP_DEEMP_2; 204 Deemphasis_RD = Deemphasis_Show; 205 PRINT_DEEMP_2; 206 break; 207 #endif 208 default: 209 break; 210 } 211 212 if (execute_test) 213 printf("The parameter is applied next measure!\n"); 214 215 } else if (received == '!') /* show config */ { 216 if (execute_test) 217 printf("Measurement is executed!\n"); 218 else 219 printf("Measurement is stopped!\n"); 220 221 DPPHYTX_Show_Cfg(); 222 } else if (received == '0') /* change sscfg */ { 223 if (SSCG == DP_SSCG_ON) { 224 SSCG = DP_SSCG_OFF; 225 PRINT_SSCG_OFF; 226 } else { 227 SSCG = DP_SSCG_ON; 228 PRINT_SSCG_ON; 229 } 230 231 /* SSCG could be applied without reset device. */ 232 if (execute_test) { 233 printf("Apply SSCG into current measurement !\n\n"); 234 TX_SSCG_Cfg = DP_TX_RDY_TEST; 235 /* TX_SSCG_Cfg |= SSCG; */ 236 TX_SSCG_Cfg |= DP_SSCG_ON; 237 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 238 } 239 } else { 240 /* Check the ESC key */ 241 if (received == 27) { 242 execute_test = 0; 243 DPTX_MCU_Reset(); 244 printf("'ESC' is pressed!\n"); 245 break; 246 } 247 248 /* If the test is execute, reset it */ 249 if (execute_test) { 250 execute_test = 0; 251 DPTX_MCU_Reset(); 252 253 printf("Stop current measurement !\n\n\n\n\n\n"); 254 } 255 256 /* Clear flag */ 257 flag = 0; 258 259 Current_Item = received; 260 261 switch (received) { 262 case 'a': 263 flag = (F_EMPHASIS_NULL | F_PAT_PRBS7); 264 break; 265 #ifdef INTERNAL 266 case 'b': 267 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 268 break; 269 270 case 'c': 271 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT); 272 break; 273 274 case 'd': /* Non-Transition Voltage Range Measurement - PLTPAT */ 275 flag = (F_EMPHASIS | F_PAT_PLTPAT); 276 break; 277 278 case 'e': /* Pre-Emphasis Level Test and Pre-Emphasis Level Delta Test- PRBS7 */ 279 flag = (F_EMPHASIS_1 | F_PAT_PRBS7); 280 break; 281 282 case 'f': /* Non-Transition Voltage Range Measurement - PRBS7 */ 283 flag = (F_EMPHASIS | F_PAT_PRBS7); 284 break; 285 286 case 'g': /* Total - PRBS7 */ 287 flag = (F_EMPHASIS_1 | F_PAT_D10_2); 288 break; 289 290 case 'h': 291 printf("Change the Swing value from request\n"); 292 flag = (F_EMPHASIS_1 | F_PAT_PRBS7 | F_SHOW_SWING); 293 break; 294 295 case 'i': 296 printf("Change the Swing value from request\n"); 297 flag = (F_EMPHASIS_1 | F_PAT_PLTPAT | DP_TX_HIGH_SPEED | F_SHOW_SWING); 298 break; 299 300 case 'j': 301 flag = F_PAT_AUX; 302 break; 303 #endif 304 case 'x': /* Auto hand shaking with DPR-100 */ 305 flag = F_EXE_AUTO; 306 break; 307 308 default: 309 printf("Non - define command!\n"); 310 break; 311 } 312 313 // Execute testing 314 if (flag) { 315 execute_test = 1; 316 GFlag = flag; 317 318 if (flag & F_PAT_AUX) { 319 printf("######################################\n"); 320 printf("#Current DP TX setting is shown below#\n"); 321 printf("######################################\n\n"); 322 323 DPPHYTX_Show_Item(Current_Item); 324 Apply_AUX_Mesument(flag); 325 } else if (flag & F_EXE_AUTO) { 326 printf("#########################\n"); 327 printf("#Enter DP TX Auto Test!!#\n"); 328 printf("#########################\n\n"); 329 330 Apply_Auto_Preset(0x1); 331 Apply_Auto_Mesument(); 332 Apply_Auto_Preset(0x0); 333 334 printf("#########################\n"); 335 printf("#Leave DP TX Auto Test!!#\n"); 336 printf("#########################\n\n"); 337 } else { 338 DPPHYTX_Show_Cfg(); 339 Apply_Main_Mesument(flag); 340 } 341 } 342 } 343 } 344 mdelay(200); 345 }; 346 347 printf("\n\n"); 348 return 0; 349 } 350 351 /* Temp for cording here */ 352 void Apply_Auto_Preset(char Init) 353 { 354 /* Fill some nessary register value for auto test */ 355 if (Init) { 356 /* Enable MCU received interrupt */ 357 writel(0x00e80000, DP_TX_INT_CLEAR); 358 359 /* Set HPD irq time interval */ 360 writel(0x04e300fb, DP_TX_IRQ_CFG); 361 362 /* Set HPD event time interval */ 363 writel(0x000007d1, DP_TX_EVENT_CFG); 364 } else { 365 /* Recover */ 366 writel(0x0, DP_TX_INT_CLEAR); 367 writel(0x0, DP_TX_IRQ_CFG); 368 writel(0x0, DP_TX_EVENT_CFG); 369 } 370 } 371 372 /* READ EDID */ 373 void Read_EDID_128(char Offset) 374 { 375 char AUX_Data[16] = {0}; 376 uchar Length = 1; 377 uchar Status = 0; 378 uchar i, j; 379 380 DBG(DBG_A_EDID, "R EDID Offset %d\n", Offset); 381 382 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 383 384 AUX_Data[0] = Offset; 385 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 386 387 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 388 389 Length = 16; 390 391 // Read 128 bytes block 392 for (i = 0; i < 8; i++) { 393 do { 394 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 395 DBG(DBG_A_EDID, "EDID read %d!\n", i); 396 397 udelay(100); 398 } while (Status == 0x20); 399 400 /* copy from temp into EDID */ 401 for (j = 0; j < 16; j++) 402 EDID[Offset + i * 16 + j] = AUX_Data[j]; 403 } 404 405 Length = 1; 406 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 407 } 408 409 void Apply_EDID_Reading(void) 410 { 411 char AUX_Data[16] = {0}; 412 uchar Length = 1; 413 uchar Status = 0; 414 415 DBG(DBG_STAGE, "Apply EDID Reading!\n"); 416 417 AUX_W(I2C_M_EA_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 418 419 AUX_W(I2C_M_CMD_W, 0x50, (int *)(&AUX_Data), &Length, &Status); 420 421 AUX_R(I2C_M_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 422 423 /* Check read EDID header */ 424 Length = 4; 425 do { 426 AUX_R(I2C_M_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 427 428 udelay(100); 429 } while (Status == 0x20); 430 431 DBG(DBG_A_EDID, "EDID First 4 is 0x%X_0x%X_0x%X_0x%X\n", AUX_Data[0], AUX_Data[1], AUX_Data[2], AUX_Data[3]); 432 433 Length = 1; 434 AUX_R(I2C_EA_CMD_R, 0x50, (int *)(&AUX_Data), &Length, &Status); 435 436 DBG(DBG_A_EDID, "Read 128!\n"); 437 Read_EDID_128(0x0); 438 439 /* If the extension bit is set, then read back next block */ 440 if (EDID[0x7E] == 0x1) { 441 DBG(DBG_A_EDID, "Read 256!\n"); 442 Read_EDID_128(0x80); 443 } 444 } 445 446 /* LINK TRAIN */ 447 uchar Adjust_CR_EQ_Train(int TrainPat, uchar ADJStatus) 448 { 449 char AUX_Data[16] = {0}; 450 uchar Ret = 0; 451 uchar Length = 1; 452 uchar Status = 0; 453 uchar AUX_R_Level = 0; 454 uchar AUX_W_Level = 0; 455 uchar DE_Level = 0x0; 456 uchar CR_Status = 0; 457 int value = 0; 458 uchar bFirst = 1; 459 uchar tempkeep = 0; 460 461 /* Set the main link pattern with TPS1 / TPS2 for Lanex_CR_Done */ 462 value = ((readl(DP_TX_MAIN_PAT) & ~(0x30000000)) | TrainPat); 463 writel(value, DP_TX_MAIN_PAT); 464 DBG(DBG_A_SUB, "1.A_C_E Set Link Pattern\n"); 465 466 /* AST phy 0xE4 Bit28 (0x1000000) / DP 0x102 Bit0 : TPS1 */ 467 /* AST phy 0xE4 Bit29 (0x2000000) / DP 0x102 Bit1 : TPS2 */ 468 if (TrainPat == 0x10000000) 469 AUX_Data[0] = 0x21; 470 else 471 AUX_Data[0] = 0x22; 472 473 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 474 DBG(DBG_A_SUB, "2.A_C_E W 0x102 set 0x%x\n", AUX_Data[0]); 475 476 /* First */ 477 if (bFirst) { 478 Length = 4; 479 480 AUX_Data[0] = CR_EQ_Keep; 481 AUX_Data[1] = CR_EQ_Keep; 482 AUX_Data[2] = CR_EQ_Keep; 483 AUX_Data[3] = CR_EQ_Keep; 484 tempkeep = CR_EQ_Keep; 485 486 do { 487 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 488 DBG(DBG_A_SUB, "3.A_C_E W 0x103 - 0x106 set\n"); 489 } while (Status == 0x20); 490 491 Length = 6; 492 493 udelay(1200); 494 495 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 496 DBG(DBG_A_SUB, "4.A_C_E R 0x200 - 0x205 read back\n"); 497 498 if ((AUX_Data[2] & ADJStatus) == ADJStatus) { 499 CR_EQ_Keep = tempkeep; 500 return Ret; 501 } 502 503 bFirst = 0; 504 } 505 506 /* loop for CR_lock */ 507 do { 508 Length = 1; 509 510 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 511 DBG(DBG_A_SUB, "5.A_C_E R 0x206 read back\n"); 512 AUX_R_Level = AUX_Data[0]; 513 514 AUX_R(AUX_CMD_R, 0x207, (int *)(&AUX_Data), &Length, &Status); 515 DBG(DBG_A_SUB, "6.A_C_E R 0x207 read back\n"); 516 517 /* Update SW Level */ 518 switch (AUX_R_Level & 0x33) { 519 case 0x00: 520 AUX_W_Level = 00; 521 break; 522 case 0x11: 523 AUX_W_Level = 01; 524 break; 525 default: 526 AUX_W_Level = 06; 527 break; 528 } 529 530 /* Update SW Level */ 531 switch (AUX_R_Level & 0xCC) { 532 case 0x00: 533 /* AUX_W_Level |= 00; */ 534 DE_Level = 0; 535 break; 536 case 0x44: 537 AUX_W_Level |= 0x08; 538 DE_Level = 1; 539 break; 540 default: 541 AUX_W_Level |= 0x30; 542 DE_Level = 2; 543 break; 544 } 545 546 /* Set the de-emphsis value */ 547 value = ((readl(DP_TX_PHY_CFG) & ~(0x33000000)) | Deemlevel[DE_Level]); 548 writel(value, DP_TX_PHY_CFG); 549 DBG(DBG_A_SUB, "6.A_C_E Set Phy config %d\n", DE_Level); 550 551 DBG(DBG_A_SUB, "Link AUX_W_Level is 0x%x\n", AUX_W_Level); 552 553 Length = 4; 554 555 AUX_Data[0] = AUX_W_Level; 556 AUX_Data[1] = AUX_W_Level; 557 AUX_Data[2] = AUX_W_Level; 558 AUX_Data[3] = AUX_W_Level; 559 tempkeep = AUX_W_Level; 560 561 do { 562 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 563 DBG(DBG_A_SUB, "7.A_C_E W 0x103 - 0x106 set\n"); 564 } while (Status == 0x20); 565 566 udelay(1380); 567 568 Length = 6; 569 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 570 DBG(DBG_A_SUB, "8.A_C_E R 0x200 - 0x205 read back\n"); 571 572 CR_Status = AUX_Data[2] & ADJStatus; 573 574 /* Decrease speed because the deemphasis level reach max value */ 575 if (AUX_W_Level == 0x36) { 576 Ret = 1; 577 break; 578 } 579 580 } while (CR_Status != ADJStatus); 581 582 CR_EQ_Keep = tempkeep; 583 584 return Ret; 585 } 586 587 uchar Link_Train_Flow(char Link_Level) 588 { 589 char AUX_Data[16] = {0}; 590 uchar Length = 1; 591 uchar Status = 0; 592 uchar Ret = 0; 593 int value = 0; 594 595 DBG(DBG_STAGE, "Link train flow! Level : %d\n", Link_Level); 596 597 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 598 DBG(DBG_A_SUB, "1.Link R 0x101 read back\n"); 599 600 /* Normal / Test case */ 601 if (Auto_Lane_Count) 602 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 603 else 604 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 605 606 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 607 DBG(DBG_A_SUB, "2.Link W 0x101 clear\n"); 608 609 /* Set different clock bit rate */ 610 value = ((readl(DP_TX_MAIN_SET) & ~(0x300)) | (Link_Level << 8)); 611 writel(value, DP_TX_MAIN_SET); 612 613 switch (Link_Level) { 614 case 0x1: /* 2.7 */ 615 AUX_Data[0] = 0x0a; 616 break; 617 618 default: /* 1.62 */ 619 AUX_Data[0] = 0x06; 620 break; 621 } 622 623 AUX_W(AUX_CMD_W, 0x100, (int *)(&AUX_Data), &Length, &Status); 624 DBG(DBG_A_SUB, "3.Link W 0x100 set\n"); 625 626 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 627 DBG(DBG_A_SUB, "4.Link R 0x101 read back\n"); 628 629 /* Normal / Test case */ 630 if (Auto_Lane_Count) 631 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 632 else 633 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 634 635 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 636 DBG(DBG_A_SUB, "5.Link W 0x101 clear\n"); 637 638 /* Set the 2 lanes and enhance frame by checking AUX 0x2 bit 7 */ 639 value = ((readl(DP_TX_MAIN_SET) & ~(0x1070)) | 0x20); 640 641 if (bEn_Frame) 642 value |= 0x1000; 643 644 writel(value, DP_TX_MAIN_SET); 645 646 value = ((readl(DP_TX_PHY_CFG) & ~(0x3000)) | 0x3000); 647 648 writel(value, DP_TX_PHY_CFG); 649 650 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 651 DBG(DBG_A_SUB, "6.Link R 0x101 read back\n"); 652 653 /* Normal / Test case */ 654 if (Auto_Lane_Count) 655 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | Auto_Lane_Count); 656 else 657 AUX_Data[0] = ((AUX_Data[0] & 0xE0) | 0x2); 658 659 AUX_W(AUX_CMD_W, 0x101, (int *)(&AUX_Data), &Length, &Status); 660 DBG(DBG_A_SUB, "7.Link W 0x101 clear\n"); 661 662 /* Set the main link control on */ 663 value = ((readl(DP_TX_PHY_SET) & ~(0x100)) | 0x100); 664 665 udelay(1000); 666 udelay(1500); 667 668 writel(value, DP_TX_PHY_SET); 669 670 do { 671 value = (readl(DP_TX_PHY_SET) & 0x200); 672 } while (value != 0x200); 673 DBG(DBG_A_SUB, "8.Link Main Link Ready\n"); 674 675 /* Adjust for CR */ 676 if (Adjust_CR_EQ_Train(0x10000000, 0x11)) { 677 Ret = 1; 678 return Ret; 679 } 680 681 /* Adjust for EQ */ 682 if (Adjust_CR_EQ_Train(0x20000000, 0x77)) { 683 Ret = 1; 684 return Ret; 685 } 686 687 return Ret; 688 } 689 690 void Apply_HPD_Normal(void) 691 { 692 char AUX_Data[16] = {0}; 693 uchar Length = 1; 694 uchar Status = 0; 695 int value = 0; 696 697 DBG(DBG_STAGE, "HPD Normal set!\n"); 698 699 AUX_Data[0] = 0x01; 700 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 701 DBG(DBG_NOR, "1.HPD_N W 0x600 set power!\n"); 702 703 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 704 DBG(DBG_NOR, "2.HPD_N R 0x0 read back is 0x%X!\n", AUX_Data[0]); 705 706 Length = 8; 707 AUX_R(AUX_CMD_R, 0x500, (int *)(&AUX_Data), &Length, &Status); 708 DBG(DBG_NOR, "3.HPD_N R 0x500 - 0x508 read back\n"); 709 710 Length = 14; 711 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 712 DBG(DBG_NOR, "4.HPD_N R 0x0 - 0xD read back\n"); 713 714 bEn_Frame = AUX_Data[2] & 0x80; 715 Link_Aux_RD_Val = AUX_Data[14]; 716 717 if (bEn_Frame) 718 DBG(DBG_NOR, "4.HPD_N R 0x2 En_Frame_Cap\n"); 719 720 Length = 1; 721 AUX_R(AUX_CMD_R, 0xe, (int *)(&AUX_Data), &Length, &Status); 722 DBG(DBG_NOR, "5.HPD_N R 0xE read back\n"); 723 724 /* Read EDID */ 725 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Enter\n"); 726 727 Apply_EDID_Reading(); 728 729 DBG(DBG_NOR, "6.HPD_N Apply_EDID_Reading Leave\n"); 730 731 Length = 2; 732 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 733 DBG(DBG_NOR, "7.HPD_N R 0x200 - 0x201 read back.\n"); 734 735 Length = 1; 736 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 737 DBG(DBG_NOR, "8.HPD_N R 0x68028 read back.\n"); 738 739 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 740 DBG(DBG_NOR, "9.HPD_N R 0x68028 read back.\n"); 741 742 AUX_R(AUX_CMD_R, 0x600, (int *)(&AUX_Data), &Length, &Status); 743 DBG(DBG_NOR, "10.HPD_N R 0x600 read back.\n"); 744 745 AUX_Data[0] = 0x01; 746 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 747 DBG(DBG_NOR, "11.HPD_N W 0x600 set power!\n"); 748 749 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Enter\n"); 750 751 Status = Link_Train_Flow(0x1); 752 753 DBG(DBG_NOR, "12.HPD_N Link_Train_Flow 0x1 Leave\n"); 754 755 if (Status) { 756 AUX_Data[0] = 0x20; 757 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 758 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x1 Fail!!\n"); 759 760 DBG(DBG_NOR, "13.HPD_N Link_Train_Flow 0x0 Enter\n"); 761 762 Status = Link_Train_Flow(0x0); 763 764 DBG(DBG_NOR, "13.HPD_NLink_Train_Flow 0x0 Leave\n"); 765 766 if (Status) { 767 AUX_Data[0] = 0x20; 768 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 769 DBG(DBG_ERR, "!!HPD_N W 0x102 set Train Flow 0x0 Fail!!\n"); 770 771 DBG(DBG_ERR, "### CAUTION!! LINK TRAN FAIL!! ###\n"); 772 773 return; 774 } 775 } 776 777 /* Link successful */ 778 AUX_Data[0] = 0x00; 779 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 780 DBG(DBG_NOR, "14.HPD_N W 0x102 clear!\n"); 781 782 /* Fill idle pattern */ 783 value = ((readl(DP_TX_MAIN_PAT) & ~(0x31000000)) | 0x01000000); 784 writel(value, DP_TX_MAIN_PAT); 785 DBG(DBG_NOR, "15.HPD_N Fill idle pattern!\n"); 786 787 Length = 1; 788 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 789 DBG(DBG_NOR, "16.HPD_N R 0x68028 read back.\n"); 790 791 Length = 5; 792 AUX_R(AUX_CMD_R, 0x68000, (int *)(&AUX_Data), &Length, &Status); 793 DBG(DBG_NOR, "17.HPD_N R 0x68000 - 0x68004 read back.\n"); 794 795 Length = 1; 796 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 797 DBG(DBG_NOR, "18.HPD_N R 0x68028 read back.\n"); 798 799 AUX_R(AUX_CMD_R, 0x68028, (int *)(&AUX_Data), &Length, &Status); 800 DBG(DBG_NOR, "19.HPD_N R 0x68028 read back.\n"); 801 802 AUX_R(AUX_CMD_R, 0x0, (int *)(&AUX_Data), &Length, &Status); 803 DBG(DBG_NOR, "20.HPD_N R 0x0 read back.\n"); 804 } 805 806 void Apply_HPD_Auto_Test(void) 807 { 808 char AUX_Data[16]; 809 uchar Length = 0; 810 uchar Status = 0; 811 uchar clear_auto_test = 0; 812 uchar auto_test_link = 0; 813 uchar auto_test_phy = 0; 814 uchar swing0 = 0, preemphasis0 = 0; 815 uchar swing1 = 0, preemphasis1 = 0; 816 int flag = 0; 817 char temp0 = 0, temp1 = 0; 818 char temp206 = 0; 819 820 DBG(DBG_STAGE, "HPD Auto test set!\n"); 821 822 /* Set power D0 */ 823 AUX_Data[0] = 0x01; 824 Length = 1; 825 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 826 DBG(DBG_A_TEST, "1.HP_I W 0x600 done!\n"); 827 828 Length = 6; 829 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 830 DBG(DBG_A_TEST, "2.HP_I R 0x200 - 0x206 done!\n"); 831 832 Length = 1; 833 AUX_R(AUX_CMD_R, 0x201, (int *)(&AUX_Data), &Length, &Status); 834 DBG(DBG_A_TEST, "3.HP_I R 0x201 : 0x%x\n", AUX_Data[0]); 835 836 /* Obtain auto test */ 837 if (AUX_Data[0] & 0x2) 838 clear_auto_test = 1; 839 else 840 clear_auto_test = 0; 841 842 /* Read dummy */ 843 Length = 3; 844 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 845 Length = 1; 846 AUX_R(AUX_CMD_R, 0x101, (int *)(&AUX_Data), &Length, &Status); 847 AUX_R(AUX_CMD_R, 0x200, (int *)(&AUX_Data), &Length, &Status); 848 Length = 3; 849 AUX_R(AUX_CMD_R, 0x202, (int *)(&AUX_Data), &Length, &Status); 850 Length = 1; 851 AUX_R(AUX_CMD_R, 0x205, (int *)(&AUX_Data), &Length, &Status); 852 DBG(DBG_A_TEST, "4. HP_I R Dummy!\n"); 853 854 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 855 DBG(DBG_A_TEST, "5. HP_I Link Rate R 0x219 : 0x%x\n", AUX_Data[0]); 856 857 if (AUX_Data[0] == 0x06) { 858 Auto_Link_Rate = AUX_Data[0]; 859 DP_Rate = DP_RATE_1_62; 860 PRINT_RATE_1_62; 861 } else if (AUX_Data[0] == 0x0a) { 862 Auto_Link_Rate = AUX_Data[0]; 863 DP_Rate = DP_RATE_2_70; 864 PRINT_RATE_2_70; 865 } else if (AUX_Data[0] == 0x14) { 866 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 867 return; 868 } 869 870 if (clear_auto_test) { 871 AUX_Data[0] = 0x02; 872 AUX_W(AUX_CMD_W, 0x201, (int *)(&AUX_Data), &Length, &Status); 873 DBG(DBG_A_TEST, "1.HP_I CA W 0x201 clear auto!\n"); 874 clear_auto_test = 0; 875 876 /* Fetch Testing data */ 877 AUX_R(AUX_CMD_R, 0x218, (int *)(&AUX_Data), &Length, &Status); 878 DBG(DBG_A_TEST, "2.HP_I CA R 0x218 : 0x%x\n", AUX_Data[0]); 879 880 /* Check auto test link flag */ 881 if (AUX_Data[0] & 0x1) 882 auto_test_link = 1; 883 else 884 auto_test_link = 0; 885 886 /* Check auto test phy flag */ 887 if (AUX_Data[0] & 0x8) 888 auto_test_phy = 1; 889 else 890 auto_test_phy = 0; 891 DBG(DBG_A_TEST, "auto test link(%d) phy(%d)\n", auto_test_link, auto_test_phy); 892 893 if (auto_test_link) { 894 AUX_R(AUX_CMD_R, 0x219, (int *)(&AUX_Data), &Length, &Status); 895 DBG(DBG_A_TEST, "1.HP_I TL R 0x219 : 0x%x\n", AUX_Data[0]); 896 897 if (AUX_Data[0] == 0x06) { 898 Auto_Link_Rate = AUX_Data[0]; 899 DP_Rate = DP_RATE_1_62; 900 PRINT_RATE_1_62; 901 } else if (AUX_Data[0] == 0x0a) { 902 Auto_Link_Rate = AUX_Data[0]; 903 DP_Rate = DP_RATE_2_70; 904 PRINT_RATE_2_70; 905 } else if (AUX_Data[0] == 0x14) { 906 DBG(DBG_ERR, "!!DON'T SET 5.4 bps !!\n"); 907 return; 908 } 909 910 AUX_R(AUX_CMD_R, 0x220, (int *)(&AUX_Data), &Length, &Status); 911 DBG(DBG_A_TEST, "2.HP_I TL R 0x220 : 0x%x\n", AUX_Data[0]); 912 Auto_Lane_Count = AUX_Data[0] & 0x1F; 913 914 AUX_Data[0] = 0x01; 915 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 916 DBG(DBG_A_TEST, "3.HP_I TL W 0x260 test ACK\n"); 917 918 mdelay(95); 919 920 /* Set power D0 */ 921 AUX_Data[0] = 0x01; 922 AUX_W(AUX_CMD_W, 0x600, (int *)(&AUX_Data), &Length, &Status); 923 DBG(DBG_A_TEST, "3.1 HP_I W 0x600 done!\n"); 924 925 switch (Auto_Link_Rate) { 926 case 0x06: 927 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Enter\n"); 928 Status = Link_Train_Flow(0x0); 929 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 1.62bps Leave\n"); 930 break; 931 932 case 0x0a: 933 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Enter\n"); 934 Status = Link_Train_Flow(0x1); 935 DBG(DBG_A_TEST, "4.HP_I TL Link_Train_Flow 2.70bps Leave\n"); 936 break; 937 938 default: 939 DBG(DBG_ERR, "!!BAD LINK RATE!!\n"); 940 return; 941 } 942 943 if (Status) { 944 DBG(DBG_ERR, "!!AUTO TEST LINK FAIL!!\n"); 945 return; 946 } 947 948 /* Link successful */ 949 AUX_Data[0] = 0x00; 950 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 951 DBG(DBG_A_TEST, "5.HP_I TL Link clear!\n"); 952 953 auto_test_link = 0; 954 } 955 956 if (auto_test_phy) { 957 Length = 1; 958 flag = 0; 959 temp206 = 0; 960 961 AUX_R(AUX_CMD_R, 0x248, (int *)(&AUX_Data), &Length, &Status); 962 DBG(DBG_A_TEST, "1.HP_I TP R 0x248 : 0x%x!\n", AUX_Data[0]); 963 964 if (AUX_Data[0] == 0x01) { 965 flag |= F_PAT_D10_2; 966 DBG(DBG_A_TEST, "HP_I TP D10.2!\n"); 967 } else if (AUX_Data[0] == 0x03) { 968 flag |= F_PAT_PRBS7; 969 DBG(DBG_A_TEST, "HP_I TP PRBS7!\n"); 970 } 971 972 AUX_R(AUX_CMD_R, 0x206, (int *)(&AUX_Data), &Length, &Status); 973 DBG(DBG_A_TEST, "2.HP_I TP R 0x206 : 0x%x!\n", AUX_Data[0]); 974 975 /* Temp for verified */ 976 DBG(DBG_INF, "Read value 0x206 : 0x%x!\n", AUX_Data[0]); 977 978 /* Check Swing */ 979 temp0 = (AUX_Data[0] & 0x03); 980 temp1 = (AUX_Data[0] & 0x30); 981 982 /* Check Swing0 */ 983 switch (temp0) { 984 case 0x2: 985 swing0 = 0x2; 986 temp206 |= 6; 987 break; 988 case 0x1: 989 swing0 = 0x1; 990 temp206 |= 1; 991 break; 992 case 0x0: 993 swing0 = 0x0; 994 break; 995 default: 996 DBG(DBG_ERR, "HP_I TP 0x206 other swing0 val %x!\n", temp0); 997 break; 998 } 999 1000 /* Check Swing1 */ 1001 switch (temp1) { 1002 case 0x20: 1003 swing1 = 0x2; 1004 temp206 |= 6; 1005 break; 1006 case 0x10: 1007 swing1 = 0x1; 1008 temp206 |= 1; 1009 break; 1010 case 0x00: 1011 swing1 = 0x0; 1012 break; 1013 default: 1014 DBG(DBG_ERR, "HP_I TP 0x206 other swing1 val %x!\n", temp1); 1015 break; 1016 } 1017 1018 if (swing0 != swing1) 1019 DBG(DBG_ERR, "Swing 0 / 1 diff val %x!\n", AUX_Data[0]); 1020 1021 /* Check Pre-emphasis */ 1022 temp0 = (AUX_Data[0] & 0x0C); 1023 temp1 = (AUX_Data[0] & 0xC0); 1024 1025 /* Check Pre-emphasis0 */ 1026 switch (temp0) { 1027 case 0x8: 1028 preemphasis0 = 0x2; 1029 temp206 |= 0x30; 1030 break; 1031 case 0x4: 1032 preemphasis0 = 0x1; 1033 temp206 |= 0x08; 1034 break; 1035 case 0x0: 1036 preemphasis0 = 0x0; 1037 break; 1038 default: 1039 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis0 val %x!\n", temp0); 1040 break; 1041 } 1042 1043 /* Check Pre-emphasis1 */ 1044 switch (temp1) { 1045 case 0x80: 1046 preemphasis1 = 0x2; 1047 temp206 |= 0x30; 1048 break; 1049 case 0x40: 1050 preemphasis1 = 0x1; 1051 temp206 |= 0x08; 1052 break; 1053 case 0x00: 1054 preemphasis1 = 0x0; 1055 break; 1056 default: 1057 DBG(DBG_ERR, "HP_I TP 0x206 other Pre-emphasis1 val %x!\n", temp1); 1058 break; 1059 } 1060 1061 if (preemphasis0 != preemphasis1) 1062 DBG(DBG_ERR, "Preemphasis 0 / 1 diff val %x!\n", AUX_Data[0]); 1063 1064 /* Judgement */ 1065 if (swing0 == 0x2 || swing1 == 0x2) 1066 Swing_Level = 0x2; 1067 else if (swing0 == 1 || swing1 == 0x1) 1068 Swing_Level = 0x1; 1069 else if (swing0 == 0x0 || swing1 == 0x0) 1070 Swing_Level = 0x0; 1071 1072 if (preemphasis0 == 0x2 || preemphasis1 == 0x2) { 1073 Deemphasis_RD = DP_DEEMP_2; 1074 Deemphasis_Level_1 = DP_DEEMP_1; 1075 DBG(DBG_ERR, "!!De-type 1 P_2 !!\n"); 1076 } else if (preemphasis0 == 0x1 || preemphasis1 == 0x1) { 1077 Deemphasis_RD = DP_DEEMP_1; 1078 Deemphasis_Level_1 = DP_DEEMP_0; 1079 DBG(DBG_ERR, "!!De-type 0 P_1 !!\n"); 1080 } else if (preemphasis0 == 0x0 || preemphasis1 == 0x0) { 1081 Deemphasis_RD = DP_DEEMP_0; 1082 Deemphasis_Level_1 = DP_DEEMP_2; 1083 DBG(DBG_ERR, "!!De-type 2 P_0 !!\n"); 1084 } 1085 1086 DBG(DBG_INF, "!!Swing %d / Pre-emphasis %d !!\n", swing0, preemphasis0); 1087 1088 flag |= F_EMPHASIS_1; 1089 1090 AUX_R(AUX_CMD_R, 0x102, (int *)(&AUX_Data), &Length, &Status); 1091 DBG(DBG_A_TEST, "3.HP_I TP R 0x102 : 0x%x\n", AUX_Data[0]); 1092 temp0 = AUX_Data[0]; 1093 1094 Length = 2; 1095 AUX_R(AUX_CMD_R, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1096 DBG(DBG_A_TEST, "4.HP_I TP R 0x10b : 0x%x\n", AUX_Data[0]); 1097 1098 AUX_W(AUX_CMD_W, 0x10b, (int *)(&AUX_Data), &Length, &Status); 1099 DBG(DBG_A_TEST, "5.HP_I TP W 0x10b done!\n"); 1100 1101 AUX_Data[0] = temp0 | 0x20; 1102 Length = 1; 1103 AUX_W(AUX_CMD_W, 0x102, (int *)(&AUX_Data), &Length, &Status); 1104 DBG(DBG_A_TEST, "6.HP_I TP W 0x102 done!\n"); 1105 1106 AUX_Data[0] = temp206; 1107 AUX_Data[1] = temp206; 1108 Length = 2; 1109 1110 do { 1111 AUX_W(AUX_CMD_W, 0x103, (int *)(&AUX_Data), &Length, &Status); 1112 DBG(DBG_A_TEST, "7.HP_I TP W 0x103 - 0x104 done!\n"); 1113 } while (Status == 0x20); 1114 1115 DPPHYTX_Show_Cfg(); 1116 Apply_Main_Mesument(flag); 1117 1118 Length = 1; 1119 AUX_Data[0] = 0x01; 1120 AUX_W(AUX_CMD_W, 0x260, (int *)(&AUX_Data), &Length, &Status); 1121 DBG(DBG_A_TEST, "8.HP_I TP W 0x260 done!\n"); 1122 1123 DBG(DBG_STAGE, "Leave Apply Auto Test\n"); 1124 1125 auto_test_phy = 0; 1126 } 1127 clear_auto_test = 0; 1128 } 1129 } 1130 1131 /* TEST SECTION */ 1132 void Apply_Auto_Mesument(void) 1133 { 1134 char auto_received = 0; 1135 int temp = 0, wdata = 0; 1136 int breakcount = 0; 1137 1138 while (1) { 1139 breakcount = 0; 1140 1141 /* Wait HPD */ 1142 do { 1143 temp = (readl(DP_TX_INT_STATUS) & 0x3800); 1144 breakcount++; 1145 1146 if (breakcount == 0x96000) { 1147 /* A simple break for esc press received */ 1148 break; 1149 } 1150 1151 } while (!(temp & 0x3800)); 1152 1153 if (temp) { 1154 /* Clear AUX write interrupt status */ 1155 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1156 writel(wdata, DP_TX_INT_CLEAR); 1157 } 1158 1159 /* Interrupt occur */ 1160 if (temp & 0x2800) { 1161 /* Initial global parameter */ 1162 Auto_Link_Rate = 0; 1163 Auto_Lane_Count = 0; 1164 bEn_Frame = 0; 1165 CR_EQ_Keep = 0; 1166 1167 if (temp & 0x2000) { 1168 printf("DP HPD irq is detected!\n"); 1169 Apply_HPD_Normal(); 1170 } 1171 1172 if (temp & 0x800) { 1173 printf("DP HPD event is detected!\n"); 1174 Apply_HPD_Auto_Test(); 1175 } 1176 } 1177 1178 /* Leave auto test if the 'ESC' is pressed */ 1179 if (tstc()) { 1180 auto_received = getc(); 1181 1182 /* Check the ESC key */ 1183 if (auto_received == 27) { 1184 printf("'ESC' is pressed under auto test!\n\n"); 1185 return; 1186 } 1187 1188 printf("DP TX auto test is executed!\n"); 1189 } 1190 } 1191 } 1192 1193 void Apply_Main_Mesument(int flag) 1194 { 1195 DPTX_MCU_Reset(); 1196 1197 /* Emphasis setting */ 1198 if (flag & F_EMPHASIS_NULL) 1199 writel(PHY_Cfg_N, DP_TX_PHY_CFG); 1200 else if (flag & F_EMPHASIS) 1201 writel(PHY_Cfg, DP_TX_PHY_CFG); 1202 else if (flag & F_EMPHASIS_1) 1203 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1204 1205 if (flag & F_RES_HIGH) 1206 writel(DP_TX_HIGH_SPEED, DP_TX_RES_CFG); 1207 else 1208 writel(DP_TX_NOR_SPEED, DP_TX_RES_CFG); 1209 1210 writel(PHY_Cfg_1, DP_TX_PHY_CFG); 1211 1212 DPPHY_Set(); 1213 1214 if (flag & F_PAT_PRBS7) 1215 Set_PRBS7(); 1216 else if (flag & F_PAT_PLTPAT) 1217 Set_PLTPAT(); 1218 else if (flag & F_PAT_HBR2CPAT) 1219 Set_HBR2CPAT(); 1220 else if (flag & F_PAT_D10_2) 1221 Set_D10_1(); 1222 1223 /* ssc special patch */ 1224 if (flag & F_PAT_D10_2) { 1225 /*Apply special patch*/ 1226 writel(0x00000400, DP_TX_RES_CFG); 1227 TX_SSCG_Cfg |= DP_SSCG_ON; 1228 } else { 1229 /*Recover into original setting*/ 1230 writel(0x00000000, DP_TX_RES_CFG); 1231 } 1232 1233 writel(TX_SSCG_Cfg, DP_TX_PHY_SET); 1234 } 1235 1236 void Apply_AUX_Mesument(int flag) 1237 { 1238 DPTX_MCU_Reset(); 1239 DPPHY_Set(); 1240 1241 writel(0x0F000000, DP_AUX_ADDR_LEN); 1242 writel(0x80000010, DP_AUX_REQ_CFG); 1243 } 1244 1245 /* FUNCTION SECTION */ 1246 /* i2c set */ 1247 #ifdef RE_DRIVER 1248 void Set_Redriver(void) 1249 { 1250 int value = 0x0; 1251 uchar offset = 0x0; 1252 uchar *set_table = &set_table0; 1253 1254 if (Deemphasis_RD == DP_DEEMP_1) 1255 set_table = &set_table1; 1256 else if (Deemphasis_RD == DP_DEEMP_2) 1257 set_table = &set_table2; 1258 1259 RD_VAL = set_table[Swing_Level]; 1260 1261 printf("RD_VAL is 0x%x\n", RD_VAL); 1262 1263 writel(0x600, I2C_BASE + I2C0_COUNT_O); 1264 value = (0x0000f0f0 | (RD_VAL << 24)); 1265 writel(value, I2C_BUFF); 1266 printf("value0 is 0x%x\n", value); 1267 value = (RD_VAL | (RD_VAL << 8) | (RD_VAL << 16) | (RD_VAL << 24)); 1268 writel(value, (I2C_BUFF + 0x4)); 1269 printf("value1 is 0x%x\n", value); 1270 writel(0x70010063, (I2C_BASE + I2C0_EXECUTE_O)); 1271 mdelay(1000); 1272 } 1273 1274 /* i2c single initial */ 1275 void I2C_L_Initial(void) 1276 { 1277 I2C_BASE = (I2C0_BASE + (I2C_DEV_OFFSET * I2C_PORT)); 1278 I2C_BUFF = (I2C0_BUFF + (I2C_BUFF_OFFSET * I2C_PORT)); 1279 1280 writel(0x0, I2C_BASE); 1281 mdelay(1); 1282 writel(0x28001, I2C_BASE); 1283 writel(0x344001, I2C_BASE + I2C0_TIMMING_O); 1284 writel(0xFFFFFFFF, I2C_BASE + I2C0_INT_STATUS_O); 1285 writel(0x0, I2C_BASE + I2C0_INT_O); 1286 mdelay(10); 1287 } 1288 1289 /* i2c golbal iniitial */ 1290 void I2C_G_Initial(void) 1291 { 1292 /* i2c multi-function */ 1293 writel(0x0FFF3000, MP_SCU410); 1294 writel(0x0F00FF00, MP_SCU414); 1295 writel(0xCFFF001F, MP_SCU418); 1296 writel(0xF00000FF, MP_SCU4b0); 1297 writel(0xF0FF00FF, MP_SCU4b4); 1298 writel(0x0000FF00, MP_SCU4b8); 1299 1300 /* I2c control */ 1301 writel(0x16, (I2C_GBASE + 0xC)); 1302 writel(0x041230C6, (I2C_GBASE + 0x10)); 1303 1304 mdelay(1000); 1305 } 1306 #endif 1307 1308 void DPTX_MCU_Reset(void) 1309 { 1310 /* Reset DPMCU & Release DPTX */ 1311 writel(0x20000000, SYS_REST); 1312 writel(0x10000000, SYS_REST_CLR); 1313 1314 /* Wait for apply setting */ 1315 mdelay(1000); 1316 } 1317 1318 void DPPHY_Set(void) 1319 { 1320 int value = 0, count = 0; 1321 1322 /* Clear power on reset */ 1323 writel(0x10000000, DP_TX_PHY_SET); 1324 mdelay(1); 1325 1326 /* Clear DPTX reset */ 1327 writel(0x11000000, DP_TX_PHY_SET); 1328 mdelay(1); 1329 1330 /* Turn on Main link / Aux channel */ 1331 writel(0x11001100, DP_TX_PHY_SET); 1332 mdelay(1); 1333 1334 while (value != DP_TX_RDY_TEST) { 1335 value = readl(DP_TX_PHY_SET); 1336 mdelay(1); 1337 count++; 1338 } 1339 } 1340 1341 char DPPHYTX_Show_Cfg(void) 1342 { 1343 char SetFail = 0; 1344 1345 PHY_Cfg = DP_PHY_INIT_CFG; 1346 PHY_Cfg_1 = DP_PHY_INIT_CFG; 1347 TX_SSCG_Cfg = DP_TX_RDY_TEST; 1348 1349 /* Show the setting */ 1350 1351 printf("######################################\n"); 1352 printf("#Current DP TX setting is shown below#\n"); 1353 printf("######################################\n\n"); 1354 1355 DPPHYTX_Show_Item(Current_Item); 1356 1357 switch (DP_Rate) { 1358 case DP_RATE_1_62: 1359 PRINT_RATE_1_62; 1360 break; 1361 1362 case DP_RATE_2_70: 1363 PRINT_RATE_2_70; 1364 break; 1365 1366 case DP_RATE_5_40: 1367 PRINT_RATE_5_40; 1368 break; 1369 1370 default: 1371 PRINT_INVALID; 1372 printf("DP Rate\n"); 1373 SetFail = 1; 1374 break; 1375 } 1376 1377 switch (Deemphasis_Show) { 1378 case DP_DEEMP_0: 1379 if (GFlag & F_SHOW_SWING) 1380 PRINT_SWING_0; 1381 else 1382 PRINT_EMPVAL_0; 1383 break; 1384 1385 case DP_DEEMP_1: 1386 if (GFlag & F_SHOW_SWING) 1387 PRINT_SWING_1; 1388 else 1389 PRINT_EMPVAL_1; 1390 break; 1391 1392 case DP_DEEMP_2: 1393 if (GFlag & F_SHOW_SWING) 1394 PRINT_SWING_2; 1395 else 1396 PRINT_EMPVAL_2; 1397 break; 1398 1399 default: 1400 PRINT_INVALID; 1401 printf("Deemphasis Level\n"); 1402 SetFail = 1; 1403 break; 1404 } 1405 1406 switch (Swing_Level) { 1407 case 0: 1408 PRINT_SWING_0; 1409 break; 1410 1411 case 1: 1412 PRINT_SWING_1; 1413 break; 1414 1415 case 2: 1416 PRINT_SWING_2; 1417 break; 1418 1419 default: 1420 PRINT_INVALID; 1421 printf("Swing Level\n"); 1422 SetFail = 1; 1423 break; 1424 } 1425 1426 PHY_Cfg = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level); 1427 PHY_Cfg_1 = DP_PHY_INIT_CFG | (DP_Rate | Deemphasis_Level_1); 1428 PHY_Cfg_N = DP_PHY_INIT_CFG | (DP_Rate | DP_DEEMP_2); 1429 1430 switch (SSCG) { 1431 case DP_SSCG_ON: 1432 /*PRINT_SSCG_ON;*/ 1433 break; 1434 1435 case DP_SSCG_OFF: 1436 /*PRINT_SSCG_OFF;*/ 1437 break; 1438 1439 default: 1440 PRINT_INVALID; 1441 printf("SSCG\n"); 1442 SetFail = 1; 1443 break; 1444 } 1445 /* TX_SSCG_Cfg |= SSCG; */ 1446 TX_SSCG_Cfg |= DP_SSCG_ON; 1447 1448 printf("\n"); 1449 1450 return SetFail; 1451 } 1452 1453 void DPPHYTX_Show_Item(char received) 1454 { 1455 switch (received) { 1456 case 'a': 1457 PRINT_ITEM_A; 1458 break; 1459 1460 case 'b': 1461 PRINT_ITEM_B; 1462 break; 1463 1464 case 'c': 1465 PRINT_ITEM_C; 1466 break; 1467 1468 case 'd': 1469 PRINT_ITEM_D; 1470 break; 1471 1472 case 'e': 1473 PRINT_ITEM_E; 1474 break; 1475 1476 case 'f': 1477 PRINT_ITEM_F; 1478 break; 1479 1480 case 'g': 1481 PRINT_ITEM_G; 1482 break; 1483 1484 case 'h': 1485 PRINT_ITEM_H; 1486 break; 1487 1488 case 'i': 1489 PRINT_ITEM_I; 1490 break; 1491 1492 case 'j': 1493 PRINT_ITEM_J; 1494 break; 1495 1496 case 'x': 1497 PRINT_ITEM_X; 1498 break; 1499 1500 default: 1501 break; 1502 } 1503 1504 printf("\n"); 1505 } 1506 1507 void Set_PRBS7(void) 1508 { 1509 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1510 writel((DP_PY_PAT | DP_PY_PAT_PRB7), DP_TX_PHY_PAT); 1511 } 1512 1513 void Set_HBR2CPAT(void) 1514 { 1515 int value = 0, count = 0; 1516 1517 writel(DP_TX_MAIN_ADV, DP_TX_MAIN_SET); 1518 1519 writel(DP_TX_PAT_HBR2, DP_TX_MAIN_PAT); 1520 writel((DP_PY_PAT | DP_PY_PAT_SCRB), DP_TX_PHY_PAT); 1521 1522 writel(DP_TX_MAIN_TRA, DP_TX_MAIN_CFG); 1523 mdelay(1); 1524 1525 while (value != DP_TX_RDY_25201) { 1526 value = (readl(DP_TX_MAIN_CFG) & 0xFFF); 1527 mdelay(1); 1528 count++; 1529 } 1530 1531 /* Reset for signal apply */ 1532 writel((DP_TX_MAIN_ADV | DP_TX_PY_RESET), DP_TX_MAIN_SET); 1533 } 1534 1535 void Set_PLTPAT(void) 1536 { 1537 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1538 1539 writel(DP_TX_PLTPAT_0, DP_TX_CUS_PAT_0); 1540 writel(DP_TX_PLTPAT_1, DP_TX_CUS_PAT_1); 1541 writel(DP_TX_PLTPAT_2, DP_TX_CUS_PAT_2); 1542 1543 writel((DP_PY_PAT | DP_PY_PAT_CUS), DP_TX_PHY_PAT); 1544 } 1545 1546 void Set_D10_1(void) 1547 { 1548 writel(DP_TX_MAIN_NOR, DP_TX_MAIN_SET); 1549 1550 writel(DP_TX_PAT_TPS1, DP_TX_MAIN_PAT); 1551 writel(DP_PY_PAT, DP_TX_PHY_PAT); 1552 } 1553 1554 uchar AUX_R(int aux_cmd, int aux_addr, int *aux_r_data, uchar *length, uchar *status) 1555 { 1556 int wdata = 0, temp = 0; 1557 uchar len = *length; 1558 1559 /* Check valid length */ 1560 if (len >= 1) 1561 len -= 1; 1562 else 1563 return 1; 1564 1565 /* Prepare AUX write address and data */ 1566 wdata = (int)((len << 24) | aux_addr); 1567 writel(wdata, DP_AUX_ADDR_LEN); 1568 1569 DBG(DBG_AUX_R, "AUX Read on 0x%x with %d bytes.\n", aux_addr, *length); 1570 1571 /* Fire AUX read */ 1572 writel(aux_cmd, DP_AUX_REQ_CFG); 1573 1574 /* Wait AUX read finish or timeout */ 1575 do { 1576 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1577 } while (!(temp & 0xC000)); 1578 1579 /* Clear AUX write interrupt status */ 1580 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1581 writel(wdata, DP_TX_INT_CLEAR); 1582 1583 if (temp & AUX_CMD_DONE) { 1584 /* Read back data count */ 1585 *aux_r_data = readl(DP_AUX_R_D_0); 1586 1587 DBG(DBG_AUX_R, "Data on 0x0 is 0x%x.\n", *aux_r_data); 1588 1589 if ((*length) > 0x4) { 1590 aux_r_data++; 1591 *aux_r_data = readl(DP_AUX_R_D_4); 1592 DBG(DBG_AUX_R, "Data on 0x4 is 0x%x.\n", *aux_r_data); 1593 } 1594 1595 if ((*length) > 0x8) { 1596 aux_r_data++; 1597 *aux_r_data = readl(DP_AUX_R_D_8); 1598 DBG(DBG_AUX_R, "Data on 0x8 is 0x%x.\n", *aux_r_data); 1599 } 1600 1601 if ((*length) > 0xC) { 1602 aux_r_data++; 1603 *aux_r_data = readl(DP_AUX_R_D_C); 1604 DBG(DBG_AUX_R, "Data on 0xC is 0x%x.\n", *aux_r_data); 1605 } 1606 1607 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1608 return 0; 1609 } else { 1610 return 1; 1611 } 1612 } 1613 1614 uchar AUX_W(int aux_cmd, int aux_addr, int *aux_w_data, uchar *length, uchar *status) 1615 { 1616 int wdata = 0, temp = 0; 1617 uchar len = *length; 1618 1619 /* Check valid length */ 1620 if (len >= 1) 1621 len -= 1; 1622 else 1623 return 1; 1624 1625 /* Prepare AUX write address and data */ 1626 wdata = (int)((len << 24) | aux_addr); 1627 writel(wdata, DP_AUX_ADDR_LEN); 1628 1629 writel(*aux_w_data, DP_AUX_W_D_0); 1630 1631 if ((*length) > 0x4) { 1632 aux_w_data++; 1633 writel(*aux_w_data, DP_AUX_W_D_4); 1634 } 1635 1636 if ((*length) > 0x8) { 1637 aux_w_data++; 1638 writel(*aux_w_data, DP_AUX_W_D_8); 1639 } 1640 1641 if ((*length) > 0xC) { 1642 aux_w_data++; 1643 writel(*aux_w_data, DP_AUX_W_D_C); 1644 } 1645 1646 /* Fire AUX write */ 1647 writel(aux_cmd, DP_AUX_REQ_CFG); 1648 1649 /* Wait AUX write finish or timeout */ 1650 do { 1651 temp = (readl(DP_TX_INT_STATUS) & 0xC000); 1652 } while (!(temp & 0xC000)); 1653 1654 /* Clear AUX write interrupt status */ 1655 wdata = (readl(DP_TX_INT_CLEAR) | (temp >> 8)); 1656 writel(wdata, DP_TX_INT_CLEAR); 1657 1658 if (temp & AUX_CMD_DONE) { 1659 (*status) = (uchar)(readl(DP_AUX_STATUS) & 0xFF); 1660 return 0; 1661 } else { 1662 return 1; 1663 } 1664 } 1665 1666 U_BOOT_CMD(dptest, 2, 0, do_ast_dptest, "ASPEED Display Port phy test", "ASPEED DP test v.0.2.9"); 1667