1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <netdev.h> 10 #include <ahci.h> 11 #include <scsi.h> 12 #include <asm/arch/clk.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/io.h> 16 #include <usb.h> 17 #include <dwc3-uboot.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 int board_init(void) 22 { 23 printf("EL Level:\tEL%d\n", current_el()); 24 25 return 0; 26 } 27 28 int board_early_init_r(void) 29 { 30 u32 val; 31 32 if (current_el() == 3) { 33 val = readl(&crlapb_base->timestamp_ref_ctrl); 34 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 35 writel(val, &crlapb_base->timestamp_ref_ctrl); 36 37 /* Program freq register in System counter */ 38 writel(zynqmp_get_system_timer_freq(), 39 &iou_scntr_secure->base_frequency_id_register); 40 /* And enable system counter */ 41 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 42 &iou_scntr_secure->counter_control_register); 43 } 44 /* Program freq register in System counter and enable system counter */ 45 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); 46 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | 47 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 48 &iou_scntr->counter_control_register); 49 50 return 0; 51 } 52 53 int dram_init(void) 54 { 55 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 56 57 return 0; 58 } 59 60 int timer_init(void) 61 { 62 return 0; 63 } 64 65 void reset_cpu(ulong addr) 66 { 67 } 68 69 #ifdef CONFIG_SCSI_AHCI_PLAT 70 void scsi_init(void) 71 { 72 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); 73 scsi_scan(1); 74 } 75 #endif 76 77 int board_late_init(void) 78 { 79 u32 reg = 0; 80 u8 bootmode; 81 82 reg = readl(&crlapb_base->boot_mode); 83 bootmode = reg & BOOT_MODES_MASK; 84 85 puts("Bootmode: "); 86 switch (bootmode) { 87 case JTAG_MODE: 88 puts("JTAG_MODE\n"); 89 setenv("modeboot", "jtagboot"); 90 break; 91 case QSPI_MODE_24BIT: 92 case QSPI_MODE_32BIT: 93 setenv("modeboot", "qspiboot"); 94 puts("QSPI_MODE\n"); 95 break; 96 case EMMC_MODE: 97 puts("EMMC_MODE\n"); 98 setenv("modeboot", "sdboot"); 99 break; 100 case SD_MODE: 101 puts("SD_MODE\n"); 102 setenv("modeboot", "sdboot"); 103 break; 104 case SD_MODE1: 105 puts("SD_MODE1\n"); 106 setenv("modeboot", "sdboot1"); 107 break; 108 case NAND_MODE: 109 puts("NAND_MODE\n"); 110 setenv("modeboot", "nandboot"); 111 break; 112 default: 113 printf("Invalid Boot Mode:0x%x\n", bootmode); 114 break; 115 } 116 117 return 0; 118 } 119 120 int checkboard(void) 121 { 122 puts("Board:\tXilinx ZynqMP\n"); 123 return 0; 124 } 125 126 #ifdef CONFIG_USB_DWC3 127 static struct dwc3_device dwc3_device_data = { 128 .maximum_speed = USB_SPEED_HIGH, 129 .base = ZYNQMP_USB0_XHCI_BASEADDR, 130 .dr_mode = USB_DR_MODE_PERIPHERAL, 131 .index = 0, 132 }; 133 134 int usb_gadget_handle_interrupts(void) 135 { 136 dwc3_uboot_handle_interrupt(0); 137 return 0; 138 } 139 140 int board_usb_init(int index, enum usb_init_type init) 141 { 142 return dwc3_uboot_init(&dwc3_device_data); 143 } 144 145 int board_usb_cleanup(int index, enum usb_init_type init) 146 { 147 dwc3_uboot_exit(index); 148 return 0; 149 } 150 #endif 151