1*84c7204bSMichal Simek /* 2*84c7204bSMichal Simek * (C) Copyright 2014 - 2015 Xilinx, Inc. 3*84c7204bSMichal Simek * Michal Simek <michal.simek@xilinx.com> 4*84c7204bSMichal Simek * 5*84c7204bSMichal Simek * SPDX-License-Identifier: GPL-2.0+ 6*84c7204bSMichal Simek */ 7*84c7204bSMichal Simek 8*84c7204bSMichal Simek #include <common.h> 9*84c7204bSMichal Simek #include <netdev.h> 10*84c7204bSMichal Simek #include <asm/arch/hardware.h> 11*84c7204bSMichal Simek #include <asm/arch/sys_proto.h> 12*84c7204bSMichal Simek #include <asm/io.h> 13*84c7204bSMichal Simek 14*84c7204bSMichal Simek DECLARE_GLOBAL_DATA_PTR; 15*84c7204bSMichal Simek 16*84c7204bSMichal Simek int board_init(void) 17*84c7204bSMichal Simek { 18*84c7204bSMichal Simek return 0; 19*84c7204bSMichal Simek } 20*84c7204bSMichal Simek 21*84c7204bSMichal Simek int board_early_init_r(void) 22*84c7204bSMichal Simek { 23*84c7204bSMichal Simek u32 val; 24*84c7204bSMichal Simek 25*84c7204bSMichal Simek val = readl(&crlapb_base->timestamp_ref_ctrl); 26*84c7204bSMichal Simek val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; 27*84c7204bSMichal Simek writel(val, &crlapb_base->timestamp_ref_ctrl); 28*84c7204bSMichal Simek 29*84c7204bSMichal Simek /* Program freq register in System counter and enable system counter */ 30*84c7204bSMichal Simek writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register); 31*84c7204bSMichal Simek writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG | 32*84c7204bSMichal Simek ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, 33*84c7204bSMichal Simek &iou_scntr->counter_control_register); 34*84c7204bSMichal Simek 35*84c7204bSMichal Simek return 0; 36*84c7204bSMichal Simek } 37*84c7204bSMichal Simek 38*84c7204bSMichal Simek int dram_init(void) 39*84c7204bSMichal Simek { 40*84c7204bSMichal Simek gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 41*84c7204bSMichal Simek 42*84c7204bSMichal Simek return 0; 43*84c7204bSMichal Simek } 44*84c7204bSMichal Simek 45*84c7204bSMichal Simek int timer_init(void) 46*84c7204bSMichal Simek { 47*84c7204bSMichal Simek return 0; 48*84c7204bSMichal Simek } 49*84c7204bSMichal Simek 50*84c7204bSMichal Simek void reset_cpu(ulong addr) 51*84c7204bSMichal Simek { 52*84c7204bSMichal Simek } 53*84c7204bSMichal Simek 54*84c7204bSMichal Simek #ifdef CONFIG_CMD_MMC 55*84c7204bSMichal Simek int board_mmc_init(bd_t *bd) 56*84c7204bSMichal Simek { 57*84c7204bSMichal Simek int ret = 0; 58*84c7204bSMichal Simek 59*84c7204bSMichal Simek #if defined(CONFIG_ZYNQ_SDHCI) 60*84c7204bSMichal Simek # if defined(CONFIG_ZYNQ_SDHCI0) 61*84c7204bSMichal Simek ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 62*84c7204bSMichal Simek # endif 63*84c7204bSMichal Simek # if defined(CONFIG_ZYNQ_SDHCI1) 64*84c7204bSMichal Simek ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 65*84c7204bSMichal Simek # endif 66*84c7204bSMichal Simek #endif 67*84c7204bSMichal Simek 68*84c7204bSMichal Simek return ret; 69*84c7204bSMichal Simek } 70*84c7204bSMichal Simek #endif 71*84c7204bSMichal Simek 72*84c7204bSMichal Simek int board_late_init(void) 73*84c7204bSMichal Simek { 74*84c7204bSMichal Simek u32 reg = 0; 75*84c7204bSMichal Simek u8 bootmode; 76*84c7204bSMichal Simek 77*84c7204bSMichal Simek reg = readl(&crlapb_base->boot_mode); 78*84c7204bSMichal Simek bootmode = reg & BOOT_MODES_MASK; 79*84c7204bSMichal Simek 80*84c7204bSMichal Simek switch (bootmode) { 81*84c7204bSMichal Simek case SD_MODE: 82*84c7204bSMichal Simek setenv("modeboot", "sdboot"); 83*84c7204bSMichal Simek break; 84*84c7204bSMichal Simek default: 85*84c7204bSMichal Simek printf("Invalid Boot Mode:0x%x\n", bootmode); 86*84c7204bSMichal Simek break; 87*84c7204bSMichal Simek } 88*84c7204bSMichal Simek 89*84c7204bSMichal Simek return 0; 90*84c7204bSMichal Simek } 91