1*ec48b6c9SMichal Simek // SPDX-License-Identifier: GPL-2.0+ 2*ec48b6c9SMichal Simek /* 3*ec48b6c9SMichal Simek * (C) Copyright 2014 - 2018 Xilinx, Inc. 4*ec48b6c9SMichal Simek * Michal Simek <michal.simek@xilinx.com> 5*ec48b6c9SMichal Simek */ 6*ec48b6c9SMichal Simek 7*ec48b6c9SMichal Simek #include <common.h> 8*ec48b6c9SMichal Simek #include <fdtdec.h> 9*ec48b6c9SMichal Simek #include <malloc.h> 10*ec48b6c9SMichal Simek #include <asm/io.h> 11*ec48b6c9SMichal Simek #include <asm/arch/hardware.h> 12*ec48b6c9SMichal Simek 13*ec48b6c9SMichal Simek DECLARE_GLOBAL_DATA_PTR; 14*ec48b6c9SMichal Simek 15*ec48b6c9SMichal Simek int board_init(void) 16*ec48b6c9SMichal Simek { 17*ec48b6c9SMichal Simek printf("EL Level:\tEL%d\n", current_el()); 18*ec48b6c9SMichal Simek 19*ec48b6c9SMichal Simek return 0; 20*ec48b6c9SMichal Simek } 21*ec48b6c9SMichal Simek 22*ec48b6c9SMichal Simek int board_early_init_r(void) 23*ec48b6c9SMichal Simek { 24*ec48b6c9SMichal Simek if (current_el() == 3) { 25*ec48b6c9SMichal Simek u32 val; 26*ec48b6c9SMichal Simek 27*ec48b6c9SMichal Simek writel(IOU_SWITCH_CTRL_CLKACT_BIT | 28*ec48b6c9SMichal Simek (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), 29*ec48b6c9SMichal Simek &crlapb_base->iou_switch_ctrl); 30*ec48b6c9SMichal Simek 31*ec48b6c9SMichal Simek /* Global timer init - Program time stamp reference clk */ 32*ec48b6c9SMichal Simek val = readl(&crlapb_base->timestamp_ref_ctrl); 33*ec48b6c9SMichal Simek val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; 34*ec48b6c9SMichal Simek writel(val, &crlapb_base->timestamp_ref_ctrl); 35*ec48b6c9SMichal Simek 36*ec48b6c9SMichal Simek debug("ref ctrl 0x%x\n", 37*ec48b6c9SMichal Simek readl(&crlapb_base->timestamp_ref_ctrl)); 38*ec48b6c9SMichal Simek 39*ec48b6c9SMichal Simek /* Clear reset of timestamp reg */ 40*ec48b6c9SMichal Simek writel(0, &crlapb_base->rst_timestamp); 41*ec48b6c9SMichal Simek 42*ec48b6c9SMichal Simek /* 43*ec48b6c9SMichal Simek * Program freq register in System counter and 44*ec48b6c9SMichal Simek * enable system counter. 45*ec48b6c9SMichal Simek */ 46*ec48b6c9SMichal Simek writel(COUNTER_FREQUENCY, 47*ec48b6c9SMichal Simek &iou_scntr_secure->base_frequency_id_register); 48*ec48b6c9SMichal Simek 49*ec48b6c9SMichal Simek debug("counter val 0x%x\n", 50*ec48b6c9SMichal Simek readl(&iou_scntr_secure->base_frequency_id_register)); 51*ec48b6c9SMichal Simek 52*ec48b6c9SMichal Simek writel(IOU_SCNTRS_CONTROL_EN, 53*ec48b6c9SMichal Simek &iou_scntr_secure->counter_control_register); 54*ec48b6c9SMichal Simek 55*ec48b6c9SMichal Simek debug("scntrs control 0x%x\n", 56*ec48b6c9SMichal Simek readl(&iou_scntr_secure->counter_control_register)); 57*ec48b6c9SMichal Simek debug("timer 0x%llx\n", get_ticks()); 58*ec48b6c9SMichal Simek debug("timer 0x%llx\n", get_ticks()); 59*ec48b6c9SMichal Simek } 60*ec48b6c9SMichal Simek 61*ec48b6c9SMichal Simek return 0; 62*ec48b6c9SMichal Simek } 63*ec48b6c9SMichal Simek 64*ec48b6c9SMichal Simek int dram_init_banksize(void) 65*ec48b6c9SMichal Simek { 66*ec48b6c9SMichal Simek fdtdec_setup_memory_banksize(); 67*ec48b6c9SMichal Simek 68*ec48b6c9SMichal Simek return 0; 69*ec48b6c9SMichal Simek } 70*ec48b6c9SMichal Simek 71*ec48b6c9SMichal Simek int dram_init(void) 72*ec48b6c9SMichal Simek { 73*ec48b6c9SMichal Simek if (fdtdec_setup_mem_size_base() != 0) 74*ec48b6c9SMichal Simek return -EINVAL; 75*ec48b6c9SMichal Simek 76*ec48b6c9SMichal Simek return 0; 77*ec48b6c9SMichal Simek } 78*ec48b6c9SMichal Simek 79*ec48b6c9SMichal Simek void reset_cpu(ulong addr) 80*ec48b6c9SMichal Simek { 81*ec48b6c9SMichal Simek } 82