1*87e29878SAndy Fleming /* 2*87e29878SAndy Fleming * Author: Adrian Cox 3*87e29878SAndy Fleming * Based on corenet_ds tlb code 4*87e29878SAndy Fleming * 5*87e29878SAndy Fleming * SPDX-License-Identifier: GPL-2.0+ 6*87e29878SAndy Fleming */ 7*87e29878SAndy Fleming 8*87e29878SAndy Fleming #include <common.h> 9*87e29878SAndy Fleming #include <asm/mmu.h> 10*87e29878SAndy Fleming 11*87e29878SAndy Fleming struct fsl_e_tlb_entry tlb_table[] = { 12*87e29878SAndy Fleming /* TLB 0 - for temp stack in cache */ 13*87e29878SAndy Fleming SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, 14*87e29878SAndy Fleming CONFIG_SYS_INIT_RAM_ADDR_PHYS, 15*87e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 16*87e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 0), 17*87e29878SAndy Fleming SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 18*87e29878SAndy Fleming CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, 19*87e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 20*87e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 0), 21*87e29878SAndy Fleming SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 22*87e29878SAndy Fleming CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, 23*87e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 24*87e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 0), 25*87e29878SAndy Fleming SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 26*87e29878SAndy Fleming CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, 27*87e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 28*87e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 0), 29*87e29878SAndy Fleming 30*87e29878SAndy Fleming /* TLB 1 */ 31*87e29878SAndy Fleming /* *I*** - Covers boot page */ 32*87e29878SAndy Fleming #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) 33*87e29878SAndy Fleming /* 34*87e29878SAndy Fleming * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the 35*87e29878SAndy Fleming * SRAM is at 0xfff00000, it covered the 0xfffff000. 36*87e29878SAndy Fleming */ 37*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, 38*87e29878SAndy Fleming MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 39*87e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_1M, 1), 40*87e29878SAndy Fleming #else 41*87e29878SAndy Fleming SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 42*87e29878SAndy Fleming MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 43*87e29878SAndy Fleming 0, 0, BOOKE_PAGESZ_4K, 1), 44*87e29878SAndy Fleming #endif 45*87e29878SAndy Fleming 46*87e29878SAndy Fleming /* *I*G* - CCSRBAR */ 47*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 48*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 49*87e29878SAndy Fleming 0, 1, BOOKE_PAGESZ_16M, 1), 50*87e29878SAndy Fleming 51*87e29878SAndy Fleming /* Local Bus */ 52*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS, 53*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 54*87e29878SAndy Fleming 0, 2, BOOKE_PAGESZ_64K, 1), 55*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS, 56*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 57*87e29878SAndy Fleming 0, 3, BOOKE_PAGESZ_4K, 1), 58*87e29878SAndy Fleming 59*87e29878SAndy Fleming /* *I*G* - PCI */ 60*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 61*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 62*87e29878SAndy Fleming 0, 4, BOOKE_PAGESZ_1G, 1), 63*87e29878SAndy Fleming 64*87e29878SAndy Fleming /* *I*G* - PCI */ 65*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, 66*87e29878SAndy Fleming CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, 67*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 68*87e29878SAndy Fleming 0, 5, BOOKE_PAGESZ_256M, 1), 69*87e29878SAndy Fleming 70*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, 71*87e29878SAndy Fleming CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, 72*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 73*87e29878SAndy Fleming 0, 6, BOOKE_PAGESZ_256M, 1), 74*87e29878SAndy Fleming 75*87e29878SAndy Fleming /* *I*G* - PCI I/O */ 76*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 77*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 78*87e29878SAndy Fleming 0, 7, BOOKE_PAGESZ_256K, 1), 79*87e29878SAndy Fleming 80*87e29878SAndy Fleming /* Bman/Qman */ 81*87e29878SAndy Fleming #ifdef CONFIG_SYS_BMAN_MEM_PHYS 82*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, 83*87e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 84*87e29878SAndy Fleming 0, 9, BOOKE_PAGESZ_1M, 1), 85*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, 86*87e29878SAndy Fleming CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, 87*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 88*87e29878SAndy Fleming 0, 10, BOOKE_PAGESZ_1M, 1), 89*87e29878SAndy Fleming #endif 90*87e29878SAndy Fleming #ifdef CONFIG_SYS_QMAN_MEM_PHYS 91*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, 92*87e29878SAndy Fleming MAS3_SW|MAS3_SR, 0, 93*87e29878SAndy Fleming 0, 11, BOOKE_PAGESZ_1M, 1), 94*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, 95*87e29878SAndy Fleming CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, 96*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 97*87e29878SAndy Fleming 0, 12, BOOKE_PAGESZ_1M, 1), 98*87e29878SAndy Fleming #endif 99*87e29878SAndy Fleming #ifdef CONFIG_SYS_DCSRBAR_PHYS 100*87e29878SAndy Fleming SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, 101*87e29878SAndy Fleming MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 102*87e29878SAndy Fleming 0, 13, BOOKE_PAGESZ_4M, 1), 103*87e29878SAndy Fleming #endif 104*87e29878SAndy Fleming }; 105*87e29878SAndy Fleming 106*87e29878SAndy Fleming int num_tlb_entries = ARRAY_SIZE(tlb_table); 107