1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2cb07d74eSMarkus Niebel/* 3cb07d74eSMarkus Niebel * Copyright (C) 2013, 2014 Markus Niebel <Markus.Niebel@tq-group.com> 4cb07d74eSMarkus Niebel * 5cb07d74eSMarkus Niebel * Refer doc/README.imximage for more details about how-to configure 6cb07d74eSMarkus Niebel * and create imximage boot image 7cb07d74eSMarkus Niebel * 8cb07d74eSMarkus Niebel * The syntax is taken as close as possible with the kwbimage 9cb07d74eSMarkus Niebel */ 10cb07d74eSMarkus Niebel 11cb07d74eSMarkus Niebel/* image version */ 12cb07d74eSMarkus NiebelIMAGE_VERSION 2 13cb07d74eSMarkus Niebel 14cb07d74eSMarkus Niebel#define __ASSEMBLY__ 15cb07d74eSMarkus Niebel#include <config.h> 16cb07d74eSMarkus Niebel 17cb07d74eSMarkus Niebel/* 18cb07d74eSMarkus Niebel * Boot Device : one of 19cb07d74eSMarkus Niebel * spi, sd (the board has no nand neither onenand) 20cb07d74eSMarkus Niebel */ 21cb07d74eSMarkus Niebel#if defined(CONFIG_TQMA6X_MMC_BOOT) 22cb07d74eSMarkus NiebelBOOT_FROM sd 23cb07d74eSMarkus Niebel#elif defined(CONFIG_TQMA6X_SPI_BOOT) 24cb07d74eSMarkus NiebelBOOT_FROM spi 25cb07d74eSMarkus Niebel#endif 26cb07d74eSMarkus Niebel 27cb07d74eSMarkus Niebel#include "asm/arch/mx6-ddr.h" 28cb07d74eSMarkus Niebel#include "asm/arch/iomux.h" 29cb07d74eSMarkus Niebel#include "asm/arch/crm_regs.h" 30cb07d74eSMarkus Niebel 31cb07d74eSMarkus Niebel/* TQMa6Q/D DDR config Rev. 0100B */ 32cb07d74eSMarkus Niebel/* IOMUX configuration */ 33cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 34cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 35cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 36cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 37cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_CAS, 0x00008030 38cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_RAS, 0x00008030 39cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 40cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 41cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 42cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 43cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 44cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 45cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 46cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 47cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 48cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 49cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 50cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 51cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 52cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 53cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 54cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 55cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 56cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 57cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 58cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 59cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 60cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 61cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_B4DS, 0x00000030 62cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_B5DS, 0x00000030 63cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_B6DS, 0x00000030 64cb07d74eSMarkus NiebelDATA 4, MX6_IOM_GRP_B7DS, 0x00000030 65cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 66cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 67cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 68cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 69cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 70cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 71cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 72cb07d74eSMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 73cb07d74eSMarkus Niebel 74cb07d74eSMarkus Niebel/* memory interface calibration values */ 75cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 76cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 77cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001B0013 78cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0018001B 79cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001B0016 80cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x0012001C 81cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x43400350 82cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x023E032C 83cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x43400348 84cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03300304 85cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x3C323436 86cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x38383242 87cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3E3C4440 88cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x4236483E 89cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 90cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 91cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 92cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 93cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 94cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 95cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 96cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 97cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 98cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 99cb07d74eSMarkus Niebel 100cb07d74eSMarkus Niebel/* configure memory interface */ 101cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 102cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 103cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDCFG0, 0x545A79B4 104cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDCFG1, 0xDB538F64 105cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 106cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 107cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 108cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 109cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDOR, 0x005A1023 110cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDASP, 0x00000027 111cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 112cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00088032 113cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 114cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 115cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x09308030 116cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 117cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDREF, 0x00005800 118cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 119cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 120cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDPDC, 0x00025536 121cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 122cb07d74eSMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 123cb07d74eSMarkus Niebel 124cb07d74eSMarkus Niebel#include "clocks.cfg" 125