1*468fb1e4SMarkus Niebel/* 2*468fb1e4SMarkus Niebel * Copyright (C) 2014 - 2015 Markus Niebel <Markus.Niebel@tq-group.com> 3*468fb1e4SMarkus Niebel * 4*468fb1e4SMarkus Niebel * SPDX-License-Identifier: GPL-2.0+ 5*468fb1e4SMarkus Niebel * 6*468fb1e4SMarkus Niebel * Refer doc/README.imximage for more details about how-to configure 7*468fb1e4SMarkus Niebel * and create imximage boot image 8*468fb1e4SMarkus Niebel * 9*468fb1e4SMarkus Niebel * The syntax is taken as close as possible with the kwbimage 10*468fb1e4SMarkus Niebel */ 11*468fb1e4SMarkus Niebel 12*468fb1e4SMarkus Niebel/* image version */ 13*468fb1e4SMarkus NiebelIMAGE_VERSION 2 14*468fb1e4SMarkus Niebel 15*468fb1e4SMarkus Niebel#define __ASSEMBLY__ 16*468fb1e4SMarkus Niebel#include <config.h> 17*468fb1e4SMarkus Niebel 18*468fb1e4SMarkus Niebel/* 19*468fb1e4SMarkus Niebel * Boot Device : one of 20*468fb1e4SMarkus Niebel * spi, sd (the board has no nand neither onenand) 21*468fb1e4SMarkus Niebel */ 22*468fb1e4SMarkus Niebel#if defined(CONFIG_TQMA6X_MMC_BOOT) 23*468fb1e4SMarkus NiebelBOOT_FROM sd 24*468fb1e4SMarkus Niebel#elif defined(CONFIG_TQMA6X_SPI_BOOT) 25*468fb1e4SMarkus NiebelBOOT_FROM spi 26*468fb1e4SMarkus Niebel#endif 27*468fb1e4SMarkus Niebel 28*468fb1e4SMarkus Niebel#include "asm/arch/mx6-ddr.h" 29*468fb1e4SMarkus Niebel#include "asm/arch/iomux.h" 30*468fb1e4SMarkus Niebel#include "asm/arch/crm_regs.h" 31*468fb1e4SMarkus Niebel 32*468fb1e4SMarkus Niebel/* TQMa6DL DDR config Rev. 0100E */ 33*468fb1e4SMarkus Niebel/* IOMUX configuration */ 34*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 35*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 36*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 37*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 38*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_CAS, 0x00008030 39*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_RAS, 0x00008030 40*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 41*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 42*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 43*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 44*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 45*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 46*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 47*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 48*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 49*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 50*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 51*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 52*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 53*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 54*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 55*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 56*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 57*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 58*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 59*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 60*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 61*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 62*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_B4DS, 0x00000030 63*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_B5DS, 0x00000030 64*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_B6DS, 0x00000030 65*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_GRP_B7DS, 0x00000030 66*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 67*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 68*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 69*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 70*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 71*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 72*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 73*468fb1e4SMarkus NiebelDATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 74*468fb1e4SMarkus Niebel 75*468fb1e4SMarkus Niebel/* memory interface calibration values */ 76*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 77*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 78*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048 79*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F 80*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D 81*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043 82*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250 83*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234 84*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C 85*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C 86*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C 87*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C 88*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36 89*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630 90*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 91*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 92*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 93*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 94*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 95*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 96*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 97*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 98*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 99*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 100*468fb1e4SMarkus Niebel 101*468fb1e4SMarkus Niebel/* configure memory interface */ 102*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D 103*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 104*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 105*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 106*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 107*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 108*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 109*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 110*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDOR, 0x00431023 111*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDASP, 0x00000027 112*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 113*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00408032 114*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 115*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 116*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 117*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 118*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDREF, 0x00007800 119*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 120*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 121*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D 122*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 123*468fb1e4SMarkus NiebelDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 124*468fb1e4SMarkus Niebel 125*468fb1e4SMarkus Niebel#include "clocks.cfg" 126