xref: /openbmc/u-boot/board/toradex/colibri_vf/dcu.c (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
280b9c3bbSStefan Agner /*
380b9c3bbSStefan Agner  * Copyright 2017 Toradex AG
480b9c3bbSStefan Agner  *
580b9c3bbSStefan Agner  * FSL DCU platform driver
680b9c3bbSStefan Agner  */
780b9c3bbSStefan Agner 
880b9c3bbSStefan Agner #include <asm/arch/crm_regs.h>
980b9c3bbSStefan Agner #include <asm/io.h>
1080b9c3bbSStefan Agner #include <common.h>
1180b9c3bbSStefan Agner #include <fsl_dcu_fb.h>
1280b9c3bbSStefan Agner #include "div64.h"
1380b9c3bbSStefan Agner 
dcu_set_pixel_clock(unsigned int pixclock)1480b9c3bbSStefan Agner unsigned int dcu_set_pixel_clock(unsigned int pixclock)
1580b9c3bbSStefan Agner {
1680b9c3bbSStefan Agner 	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
1780b9c3bbSStefan Agner 	unsigned long long div;
1880b9c3bbSStefan Agner 
1980b9c3bbSStefan Agner 	clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
2080b9c3bbSStefan Agner 	clrsetbits_le32(&ccm->cscdr3,
2180b9c3bbSStefan Agner 			CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
2280b9c3bbSStefan Agner 			CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
2380b9c3bbSStefan Agner 	div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
2480b9c3bbSStefan Agner 	do_div(div, pixclock);
2580b9c3bbSStefan Agner 
2680b9c3bbSStefan Agner 	return div;
2780b9c3bbSStefan Agner }
2880b9c3bbSStefan Agner 
platform_dcu_init(unsigned int xres,unsigned int yres,const char * port,struct fb_videomode * dcu_fb_videomode)2980b9c3bbSStefan Agner int platform_dcu_init(unsigned int xres, unsigned int yres,
3080b9c3bbSStefan Agner 		      const char *port,
3180b9c3bbSStefan Agner 		      struct fb_videomode *dcu_fb_videomode)
3280b9c3bbSStefan Agner {
3380b9c3bbSStefan Agner 	fsl_dcu_init(xres, yres, 32);
3480b9c3bbSStefan Agner 
3580b9c3bbSStefan Agner 	return 0;
3680b9c3bbSStefan Agner }
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