1 /* 2 * K2E EVM : Board initialization 3 * 4 * (C) Copyright 2014 5 * Texas Instruments Incorporated, <www.ti.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/ddr3.h> 12 #include <asm/arch/hardware.h> 13 #include <asm/ti-common/keystone_net.h> 14 15 unsigned int get_external_clk(u32 clk) 16 { 17 unsigned int clk_freq; 18 19 switch (clk) { 20 case sys_clk: 21 clk_freq = 100000000; 22 break; 23 case alt_core_clk: 24 clk_freq = 100000000; 25 break; 26 case pa_clk: 27 clk_freq = 100000000; 28 break; 29 case ddr3a_clk: 30 clk_freq = 100000000; 31 break; 32 default: 33 clk_freq = 0; 34 break; 35 } 36 37 return clk_freq; 38 } 39 40 static struct pll_init_data core_pll_config[NUM_SPDS] = { 41 [SPD800] = CORE_PLL_800, 42 [SPD850] = CORE_PLL_850, 43 [SPD1000] = CORE_PLL_1000, 44 [SPD1250] = CORE_PLL_1250, 45 [SPD1350] = CORE_PLL_1350, 46 [SPD1400] = CORE_PLL_1400, 47 [SPD1500] = CORE_PLL_1500, 48 }; 49 50 /* DEV and ARM speed definitions as specified in DEVSPEED register */ 51 int speeds[DEVSPEED_NUMSPDS] = { 52 SPD850, 53 SPD1000, 54 SPD1250, 55 SPD1350, 56 SPD1400, 57 SPD1500, 58 SPD1400, 59 SPD1350, 60 SPD1250, 61 SPD1000, 62 SPD850, 63 SPD800, 64 }; 65 66 s16 divn_val[16] = { 67 0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 68 }; 69 70 static struct pll_init_data pa_pll_config = 71 PASS_PLL_1000; 72 73 struct pll_init_data *get_pll_init_data(int pll) 74 { 75 int speed; 76 struct pll_init_data *data; 77 78 switch (pll) { 79 case MAIN_PLL: 80 speed = get_max_dev_speed(speeds); 81 data = &core_pll_config[speed]; 82 break; 83 case PASS_PLL: 84 data = &pa_pll_config; 85 break; 86 default: 87 data = NULL; 88 } 89 90 return data; 91 } 92 93 #ifdef CONFIG_DRIVER_TI_KEYSTONE_NET 94 struct eth_priv_t eth_priv_cfg[] = { 95 { 96 .int_name = "K2E_EMAC0", 97 .rx_flow = 0, 98 .phy_addr = 0, 99 .slave_port = 1, 100 .sgmii_link_type = SGMII_LINK_MAC_PHY, 101 .phy_if = PHY_INTERFACE_MODE_SGMII, 102 }, 103 { 104 .int_name = "K2E_EMAC1", 105 .rx_flow = 8, 106 .phy_addr = 1, 107 .slave_port = 2, 108 .sgmii_link_type = SGMII_LINK_MAC_PHY, 109 .phy_if = PHY_INTERFACE_MODE_SGMII, 110 }, 111 { 112 .int_name = "K2E_EMAC2", 113 .rx_flow = 16, 114 .phy_addr = 2, 115 .slave_port = 3, 116 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 117 .phy_if = PHY_INTERFACE_MODE_SGMII, 118 }, 119 { 120 .int_name = "K2E_EMAC3", 121 .rx_flow = 24, 122 .phy_addr = 3, 123 .slave_port = 4, 124 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 125 .phy_if = PHY_INTERFACE_MODE_SGMII, 126 }, 127 { 128 .int_name = "K2E_EMAC4", 129 .rx_flow = 32, 130 .phy_addr = 4, 131 .slave_port = 5, 132 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 133 .phy_if = PHY_INTERFACE_MODE_SGMII, 134 }, 135 { 136 .int_name = "K2E_EMAC5", 137 .rx_flow = 40, 138 .phy_addr = 5, 139 .slave_port = 6, 140 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 141 .phy_if = PHY_INTERFACE_MODE_SGMII, 142 }, 143 { 144 .int_name = "K2E_EMAC6", 145 .rx_flow = 48, 146 .phy_addr = 6, 147 .slave_port = 7, 148 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 149 .phy_if = PHY_INTERFACE_MODE_SGMII, 150 }, 151 { 152 .int_name = "K2E_EMAC7", 153 .rx_flow = 56, 154 .phy_addr = 7, 155 .slave_port = 8, 156 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, 157 .phy_if = PHY_INTERFACE_MODE_SGMII, 158 }, 159 }; 160 161 int get_num_eth_ports(void) 162 { 163 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); 164 } 165 #endif 166 167 #if defined(CONFIG_MULTI_DTB_FIT) 168 int board_fit_config_name_match(const char *name) 169 { 170 if (!strcmp(name, "keystone-k2e-evm")) 171 return 0; 172 173 return -1; 174 } 175 #endif 176 177 #if defined(CONFIG_BOARD_EARLY_INIT_F) 178 int board_early_init_f(void) 179 { 180 init_plls(); 181 182 return 0; 183 } 184 #endif 185 186 #ifdef CONFIG_SPL_BUILD 187 void spl_init_keystone_plls(void) 188 { 189 init_plls(); 190 } 191 #endif 192