1 /* 2 * (C) Copyright 2013 3 * Texas Instruments Incorporated, <www.ti.com> 4 * 5 * Lokesh Vutla <lokeshvutla@ti.com> 6 * 7 * Based on previous work by: 8 * Aneesh V <aneesh@ti.com> 9 * Steve Sakoman <steve@sakoman.com> 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #include <common.h> 14 #include <palmas.h> 15 #include <sata.h> 16 #include <asm/gpio.h> 17 #include <usb.h> 18 #include <linux/usb/gadget.h> 19 #include <asm/arch/gpio.h> 20 #include <asm/arch/sys_proto.h> 21 #include <asm/arch/mmc_host_def.h> 22 #include <asm/arch/sata.h> 23 #include <environment.h> 24 #include <dwc3-uboot.h> 25 #include <dwc3-omap-uboot.h> 26 #include <ti-usb-phy-uboot.h> 27 28 #include "mux_data.h" 29 30 #ifdef CONFIG_DRIVER_TI_CPSW 31 #include <cpsw.h> 32 #endif 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 /* GPIO 7_11 */ 37 #define GPIO_DDR_VTT_EN 203 38 39 const struct omap_sysinfo sysinfo = { 40 "Board: DRA7xx\n" 41 }; 42 43 /* 44 * Adjust I/O delays on the Tx control and data lines of each MAC port. This 45 * is a workaround in order to work properly with the DP83865 PHYs on the EVM. 46 * In 3COM RGMII mode this PHY applies it's own internal clock delay, so we 47 * essentially need to counteract the DRA7xx internal delay, and we do this 48 * by delaying the control and data lines. If not using this PHY, you probably 49 * don't need to do this stuff! 50 */ 51 static void dra7xx_adj_io_delay(const struct io_delay *io_dly) 52 { 53 int i = 0; 54 u32 reg_val; 55 u32 delta; 56 u32 coarse; 57 u32 fine; 58 59 writel(CFG_IO_DELAY_UNLOCK_KEY, CFG_IO_DELAY_LOCK); 60 61 while(io_dly[i].addr) { 62 writel(CFG_IO_DELAY_ACCESS_PATTERN & ~CFG_IO_DELAY_LOCK_MASK, 63 io_dly[i].addr); 64 delta = io_dly[i].dly; 65 reg_val = readl(io_dly[i].addr) & 0x3ff; 66 coarse = ((reg_val >> 5) & 0x1F) + ((delta >> 5) & 0x1F); 67 coarse = (coarse > 0x1F) ? (0x1F) : (coarse); 68 fine = (reg_val & 0x1F) + (delta & 0x1F); 69 fine = (fine > 0x1F) ? (0x1F) : (fine); 70 reg_val = CFG_IO_DELAY_ACCESS_PATTERN | 71 CFG_IO_DELAY_LOCK_MASK | 72 ((coarse << 5) | (fine)); 73 writel(reg_val, io_dly[i].addr); 74 i++; 75 } 76 77 writel(CFG_IO_DELAY_LOCK_KEY, CFG_IO_DELAY_LOCK); 78 } 79 80 /** 81 * @brief board_init 82 * 83 * @return 0 84 */ 85 int board_init(void) 86 { 87 gpmc_init(); 88 gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ 89 90 return 0; 91 } 92 93 int board_late_init(void) 94 { 95 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 96 u32 id[4]; 97 98 if (omap_revision() == DRA722_ES1_0) 99 setenv("board_name", "dra72x"); 100 else 101 setenv("board_name", "dra7xx"); 102 103 id[0] = readl((*ctrl)->control_std_fuse_die_id_0); 104 id[1] = readl((*ctrl)->control_std_fuse_die_id_1); 105 usb_set_serial_num_from_die_id(id); 106 #endif 107 return 0; 108 } 109 110 static void do_set_mux32(u32 base, 111 struct pad_conf_entry const *array, int size) 112 { 113 int i; 114 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 115 116 for (i = 0; i < size; i++, pad++) 117 writel(pad->val, base + pad->offset); 118 } 119 120 void set_muxconf_regs_essential(void) 121 { 122 do_set_mux32((*ctrl)->control_padconf_core_base, 123 core_padconf_array_essential, 124 sizeof(core_padconf_array_essential) / 125 sizeof(struct pad_conf_entry)); 126 } 127 128 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) 129 int board_mmc_init(bd_t *bis) 130 { 131 omap_mmc_init(0, 0, 0, -1, -1); 132 omap_mmc_init(1, 0, 0, -1, -1); 133 return 0; 134 } 135 #endif 136 137 #ifdef CONFIG_USB_DWC3 138 static struct dwc3_device usb_otg_ss1 = { 139 .maximum_speed = USB_SPEED_SUPER, 140 .base = DRA7_USB_OTG_SS1_BASE, 141 .tx_fifo_resize = false, 142 .index = 0, 143 }; 144 145 static struct dwc3_omap_device usb_otg_ss1_glue = { 146 .base = (void *)DRA7_USB_OTG_SS1_GLUE_BASE, 147 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 148 .vbus_id_status = OMAP_DWC3_VBUS_VALID, 149 .index = 0, 150 }; 151 152 static struct ti_usb_phy_device usb_phy1_device = { 153 .pll_ctrl_base = (void *)DRA7_USB3_PHY1_PLL_CTRL, 154 .usb2_phy_power = (void *)DRA7_USB2_PHY1_POWER, 155 .usb3_phy_power = (void *)DRA7_USB3_PHY1_POWER, 156 .index = 0, 157 }; 158 159 static struct dwc3_device usb_otg_ss2 = { 160 .maximum_speed = USB_SPEED_SUPER, 161 .base = DRA7_USB_OTG_SS2_BASE, 162 .tx_fifo_resize = false, 163 .index = 1, 164 }; 165 166 static struct dwc3_omap_device usb_otg_ss2_glue = { 167 .base = (void *)DRA7_USB_OTG_SS2_GLUE_BASE, 168 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 169 .vbus_id_status = OMAP_DWC3_VBUS_VALID, 170 .index = 1, 171 }; 172 173 static struct ti_usb_phy_device usb_phy2_device = { 174 .usb2_phy_power = (void *)DRA7_USB2_PHY2_POWER, 175 .index = 1, 176 }; 177 178 int board_usb_init(int index, enum usb_init_type init) 179 { 180 switch (index) { 181 case 0: 182 if (init == USB_INIT_DEVICE) { 183 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 184 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 185 } else { 186 usb_otg_ss1.dr_mode = USB_DR_MODE_HOST; 187 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 188 } 189 190 ti_usb_phy_uboot_init(&usb_phy1_device); 191 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 192 dwc3_uboot_init(&usb_otg_ss1); 193 break; 194 case 1: 195 if (init == USB_INIT_DEVICE) { 196 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 197 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 198 } else { 199 usb_otg_ss2.dr_mode = USB_DR_MODE_HOST; 200 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_ID_GROUND; 201 } 202 203 ti_usb_phy_uboot_init(&usb_phy2_device); 204 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 205 dwc3_uboot_init(&usb_otg_ss2); 206 break; 207 default: 208 printf("Invalid Controller Index\n"); 209 } 210 211 return 0; 212 } 213 214 int board_usb_cleanup(int index, enum usb_init_type init) 215 { 216 switch (index) { 217 case 0: 218 case 1: 219 ti_usb_phy_uboot_exit(index); 220 dwc3_uboot_exit(index); 221 dwc3_omap_uboot_exit(index); 222 break; 223 default: 224 printf("Invalid Controller Index\n"); 225 } 226 return 0; 227 } 228 229 int usb_gadget_handle_interrupts(int index) 230 { 231 u32 status; 232 233 status = dwc3_omap_uboot_interrupt_status(index); 234 if (status) 235 dwc3_uboot_handle_interrupt(index); 236 237 return 0; 238 } 239 #endif 240 241 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) 242 int spl_start_uboot(void) 243 { 244 /* break into full u-boot on 'c' */ 245 if (serial_tstc() && serial_getc() == 'c') 246 return 1; 247 248 #ifdef CONFIG_SPL_ENV_SUPPORT 249 env_init(); 250 env_relocate_spec(); 251 if (getenv_yesno("boot_os") != 1) 252 return 1; 253 #endif 254 255 return 0; 256 } 257 #endif 258 259 #ifdef CONFIG_DRIVER_TI_CPSW 260 261 /* Delay value to add to calibrated value */ 262 #define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) 263 #define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) 264 #define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) 265 #define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) 266 #define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) 267 #define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) 268 #define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) 269 #define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) 270 #define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) 271 #define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0) 272 273 extern u32 *const omap_si_rev; 274 275 static void cpsw_control(int enabled) 276 { 277 /* VTP can be added here */ 278 279 return; 280 } 281 282 static struct cpsw_slave_data cpsw_slaves[] = { 283 { 284 .slave_reg_ofs = 0x208, 285 .sliver_reg_ofs = 0xd80, 286 .phy_addr = 2, 287 }, 288 { 289 .slave_reg_ofs = 0x308, 290 .sliver_reg_ofs = 0xdc0, 291 .phy_addr = 3, 292 }, 293 }; 294 295 static struct cpsw_platform_data cpsw_data = { 296 .mdio_base = CPSW_MDIO_BASE, 297 .cpsw_base = CPSW_BASE, 298 .mdio_div = 0xff, 299 .channels = 8, 300 .cpdma_reg_ofs = 0x800, 301 .slaves = 2, 302 .slave_data = cpsw_slaves, 303 .ale_reg_ofs = 0xd00, 304 .ale_entries = 1024, 305 .host_port_reg_ofs = 0x108, 306 .hw_stats_reg_ofs = 0x900, 307 .bd_ram_ofs = 0x2000, 308 .mac_control = (1 << 5), 309 .control = cpsw_control, 310 .host_port_num = 0, 311 .version = CPSW_CTRL_VERSION_2, 312 }; 313 314 int board_eth_init(bd_t *bis) 315 { 316 int ret; 317 uint8_t mac_addr[6]; 318 uint32_t mac_hi, mac_lo; 319 uint32_t ctrl_val; 320 const struct io_delay io_dly[] = { 321 {CFG_RGMII0_TXCTL, RGMII0_TXCTL_DLY_VAL}, 322 {CFG_RGMII0_TXD0, RGMII0_TXD0_DLY_VAL}, 323 {CFG_RGMII0_TXD1, RGMII0_TXD1_DLY_VAL}, 324 {CFG_RGMII0_TXD2, RGMII0_TXD2_DLY_VAL}, 325 {CFG_RGMII0_TXD3, RGMII0_TXD3_DLY_VAL}, 326 {CFG_VIN2A_D13, VIN2A_D13_DLY_VAL}, 327 {CFG_VIN2A_D17, VIN2A_D17_DLY_VAL}, 328 {CFG_VIN2A_D16, VIN2A_D16_DLY_VAL}, 329 {CFG_VIN2A_D15, VIN2A_D15_DLY_VAL}, 330 {CFG_VIN2A_D14, VIN2A_D14_DLY_VAL}, 331 {0} 332 }; 333 334 /* Adjust IO delay for RGMII tx path */ 335 dra7xx_adj_io_delay(io_dly); 336 337 /* try reading mac address from efuse */ 338 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); 339 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); 340 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 341 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 342 mac_addr[2] = mac_hi & 0xFF; 343 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 344 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 345 mac_addr[5] = mac_lo & 0xFF; 346 347 if (!getenv("ethaddr")) { 348 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 349 350 if (is_valid_ethaddr(mac_addr)) 351 eth_setenv_enetaddr("ethaddr", mac_addr); 352 } 353 354 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); 355 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); 356 mac_addr[0] = (mac_hi & 0xFF0000) >> 16; 357 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 358 mac_addr[2] = mac_hi & 0xFF; 359 mac_addr[3] = (mac_lo & 0xFF0000) >> 16; 360 mac_addr[4] = (mac_lo & 0xFF00) >> 8; 361 mac_addr[5] = mac_lo & 0xFF; 362 363 if (!getenv("eth1addr")) { 364 if (is_valid_ethaddr(mac_addr)) 365 eth_setenv_enetaddr("eth1addr", mac_addr); 366 } 367 368 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); 369 ctrl_val |= 0x22; 370 writel(ctrl_val, (*ctrl)->control_core_control_io1); 371 372 if (*omap_si_rev == DRA722_ES1_0) 373 cpsw_data.active_slave = 1; 374 375 ret = cpsw_register(&cpsw_data); 376 if (ret < 0) 377 printf("Error %d registering CPSW switch\n", ret); 378 379 return ret; 380 } 381 #endif 382 383 #ifdef CONFIG_BOARD_EARLY_INIT_F 384 /* VTT regulator enable */ 385 static inline void vtt_regulator_enable(void) 386 { 387 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) 388 return; 389 390 /* Do not enable VTT for DRA722 */ 391 if (omap_revision() == DRA722_ES1_0) 392 return; 393 394 /* 395 * EVM Rev G and later use gpio7_11 for DDR3 termination. 396 * This is safe enough to do on older revs. 397 */ 398 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 399 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 400 } 401 402 int board_early_init_f(void) 403 { 404 vtt_regulator_enable(); 405 return 0; 406 } 407 #endif 408