10911d952SLokesh Vutla // SPDX-License-Identifier: GPL-2.0+ 20911d952SLokesh Vutla /* 30911d952SLokesh Vutla * Board specific initialization for AM654 EVM 40911d952SLokesh Vutla * 50911d952SLokesh Vutla * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ 60911d952SLokesh Vutla * Lokesh Vutla <lokeshvutla@ti.com> 70911d952SLokesh Vutla * 80911d952SLokesh Vutla */ 90911d952SLokesh Vutla 100911d952SLokesh Vutla #include <common.h> 110911d952SLokesh Vutla #include <asm/io.h> 120911d952SLokesh Vutla #include <spl.h> 130911d952SLokesh Vutla 140911d952SLokesh Vutla DECLARE_GLOBAL_DATA_PTR; 150911d952SLokesh Vutla board_init(void)160911d952SLokesh Vutlaint board_init(void) 170911d952SLokesh Vutla { 180911d952SLokesh Vutla return 0; 190911d952SLokesh Vutla } 200911d952SLokesh Vutla dram_init(void)210911d952SLokesh Vutlaint dram_init(void) 220911d952SLokesh Vutla { 230911d952SLokesh Vutla #ifdef CONFIG_PHYS_64BIT 240911d952SLokesh Vutla gd->ram_size = 0x100000000; 250911d952SLokesh Vutla #else 260911d952SLokesh Vutla gd->ram_size = 0x80000000; 270911d952SLokesh Vutla #endif 280911d952SLokesh Vutla 290911d952SLokesh Vutla return 0; 300911d952SLokesh Vutla } 310911d952SLokesh Vutla board_get_usable_ram_top(ulong total_size)320911d952SLokesh Vutlaulong board_get_usable_ram_top(ulong total_size) 330911d952SLokesh Vutla { 340911d952SLokesh Vutla #ifdef CONFIG_PHYS_64BIT 350911d952SLokesh Vutla /* Limit RAM used by U-Boot to the DDR low region */ 360911d952SLokesh Vutla if (gd->ram_top > 0x100000000) 370911d952SLokesh Vutla return 0x100000000; 380911d952SLokesh Vutla #endif 390911d952SLokesh Vutla 400911d952SLokesh Vutla return gd->ram_top; 410911d952SLokesh Vutla } 420911d952SLokesh Vutla dram_init_banksize(void)430911d952SLokesh Vutlaint dram_init_banksize(void) 440911d952SLokesh Vutla { 450911d952SLokesh Vutla /* Bank 0 declares the memory available in the DDR low region */ 460911d952SLokesh Vutla gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 470911d952SLokesh Vutla gd->bd->bi_dram[0].size = 0x80000000; 480911d952SLokesh Vutla 490911d952SLokesh Vutla #ifdef CONFIG_PHYS_64BIT 500911d952SLokesh Vutla /* Bank 1 declares the memory available in the DDR high region */ 510911d952SLokesh Vutla gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1; 520911d952SLokesh Vutla gd->bd->bi_dram[1].size = 0x80000000; 530911d952SLokesh Vutla #endif 540911d952SLokesh Vutla 550911d952SLokesh Vutla return 0; 560911d952SLokesh Vutla } 57*ea8ad1d9SLokesh Vutla 58*ea8ad1d9SLokesh Vutla #ifdef CONFIG_SPL_LOAD_FIT board_fit_config_name_match(const char * name)59*ea8ad1d9SLokesh Vutlaint board_fit_config_name_match(const char *name) 60*ea8ad1d9SLokesh Vutla { 61*ea8ad1d9SLokesh Vutla #ifdef CONFIG_TARGET_AM654_A53_EVM 62*ea8ad1d9SLokesh Vutla if (!strcmp(name, "k3-am654-base-board")) 63*ea8ad1d9SLokesh Vutla return 0; 64*ea8ad1d9SLokesh Vutla #endif 65*ea8ad1d9SLokesh Vutla 66*ea8ad1d9SLokesh Vutla return -1; 67*ea8ad1d9SLokesh Vutla } 68*ea8ad1d9SLokesh Vutla #endif 69