1 /* 2 * board.c 3 * 4 * Board functions for TI AM43XX based boards 5 * 6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <environment.h> 13 #include <i2c.h> 14 #include <linux/errno.h> 15 #include <spl.h> 16 #include <usb.h> 17 #include <asm/omap_sec_common.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/arch/mux.h> 21 #include <asm/arch/ddr_defs.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/emif.h> 24 #include <asm/omap_common.h> 25 #include "../common/board_detect.h" 26 #include "board.h" 27 #include <power/pmic.h> 28 #include <power/tps65218.h> 29 #include <power/tps62362.h> 30 #include <miiphy.h> 31 #include <cpsw.h> 32 #include <linux/usb/gadget.h> 33 #include <dwc3-uboot.h> 34 #include <dwc3-omap-uboot.h> 35 #include <ti-usb-phy-uboot.h> 36 37 DECLARE_GLOBAL_DATA_PTR; 38 39 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 40 41 /* 42 * Read header information from EEPROM into global structure. 43 */ 44 #ifdef CONFIG_TI_I2C_BOARD_DETECT 45 void do_board_detect(void) 46 { 47 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 48 CONFIG_EEPROM_CHIP_ADDRESS)) 49 printf("ti_i2c_eeprom_init failed\n"); 50 } 51 #endif 52 53 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 54 55 const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = { 56 { /* 19.2 MHz */ 57 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */ 58 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 59 {125, 3, 1, -1, -1, -1, -1}, /* OPP 100 */ 60 {150, 3, 1, -1, -1, -1, -1}, /* OPP 120 */ 61 {125, 2, 1, -1, -1, -1, -1}, /* OPP TB */ 62 {625, 11, 1, -1, -1, -1, -1} /* OPP NT */ 63 }, 64 { /* 24 MHz */ 65 {300, 23, 1, -1, -1, -1, -1}, /* OPP 50 */ 66 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 67 {600, 23, 1, -1, -1, -1, -1}, /* OPP 100 */ 68 {720, 23, 1, -1, -1, -1, -1}, /* OPP 120 */ 69 {800, 23, 1, -1, -1, -1, -1}, /* OPP TB */ 70 {1000, 23, 1, -1, -1, -1, -1} /* OPP NT */ 71 }, 72 { /* 25 MHz */ 73 {300, 24, 1, -1, -1, -1, -1}, /* OPP 50 */ 74 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 75 {600, 24, 1, -1, -1, -1, -1}, /* OPP 100 */ 76 {720, 24, 1, -1, -1, -1, -1}, /* OPP 120 */ 77 {800, 24, 1, -1, -1, -1, -1}, /* OPP TB */ 78 {1000, 24, 1, -1, -1, -1, -1} /* OPP NT */ 79 }, 80 { /* 26 MHz */ 81 {300, 25, 1, -1, -1, -1, -1}, /* OPP 50 */ 82 {-1, -1, -1, -1, -1, -1, -1}, /* OPP RESERVED */ 83 {600, 25, 1, -1, -1, -1, -1}, /* OPP 100 */ 84 {720, 25, 1, -1, -1, -1, -1}, /* OPP 120 */ 85 {800, 25, 1, -1, -1, -1, -1}, /* OPP TB */ 86 {1000, 25, 1, -1, -1, -1, -1} /* OPP NT */ 87 }, 88 }; 89 90 const struct dpll_params dpll_core[NUM_CRYSTAL_FREQ] = { 91 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */ 92 {1000, 23, -1, -1, 10, 8, 4}, /* 24 MHz */ 93 {1000, 24, -1, -1, 10, 8, 4}, /* 25 MHz */ 94 {1000, 25, -1, -1, 10, 8, 4} /* 26 MHz */ 95 }; 96 97 const struct dpll_params dpll_per[NUM_CRYSTAL_FREQ] = { 98 {400, 7, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 99 {400, 9, 5, -1, -1, -1, -1}, /* 24 MHz */ 100 {384, 9, 5, -1, -1, -1, -1}, /* 25 MHz */ 101 {480, 12, 5, -1, -1, -1, -1} /* 26 MHz */ 102 }; 103 104 const struct dpll_params epos_evm_dpll_ddr[NUM_CRYSTAL_FREQ] = { 105 {665, 47, 1, -1, 4, -1, -1}, /*19.2*/ 106 {133, 11, 1, -1, 4, -1, -1}, /* 24 MHz */ 107 {266, 24, 1, -1, 4, -1, -1}, /* 25 MHz */ 108 {133, 12, 1, -1, 4, -1, -1} /* 26 MHz */ 109 }; 110 111 const struct dpll_params gp_evm_dpll_ddr = { 112 50, 2, 1, -1, 2, -1, -1}; 113 114 static const struct dpll_params idk_dpll_ddr = { 115 400, 23, 1, -1, 2, -1, -1 116 }; 117 118 static const u32 ext_phy_ctrl_const_base_lpddr2[] = { 119 0x00500050, 120 0x00350035, 121 0x00350035, 122 0x00350035, 123 0x00350035, 124 0x00350035, 125 0x00000000, 126 0x00000000, 127 0x00000000, 128 0x00000000, 129 0x00000000, 130 0x00000000, 131 0x00000000, 132 0x00000000, 133 0x00000000, 134 0x00000000, 135 0x00000000, 136 0x00000000, 137 0x40001000, 138 0x08102040 139 }; 140 141 const struct ctrl_ioregs ioregs_lpddr2 = { 142 .cm0ioctl = LPDDR2_ADDRCTRL_IOCTRL_VALUE, 143 .cm1ioctl = LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE, 144 .cm2ioctl = LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE, 145 .dt0ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 146 .dt1ioctl = LPDDR2_DATA0_IOCTRL_VALUE, 147 .dt2ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 148 .dt3ioctrl = LPDDR2_DATA0_IOCTRL_VALUE, 149 .emif_sdram_config_ext = 0x1, 150 }; 151 152 const struct emif_regs emif_regs_lpddr2 = { 153 .sdram_config = 0x808012BA, 154 .ref_ctrl = 0x0000040D, 155 .sdram_tim1 = 0xEA86B411, 156 .sdram_tim2 = 0x103A094A, 157 .sdram_tim3 = 0x0F6BA37F, 158 .read_idle_ctrl = 0x00050000, 159 .zq_config = 0x50074BE4, 160 .temp_alert_config = 0x0, 161 .emif_rd_wr_lvl_rmp_win = 0x0, 162 .emif_rd_wr_lvl_rmp_ctl = 0x0, 163 .emif_rd_wr_lvl_ctl = 0x0, 164 .emif_ddr_phy_ctlr_1 = 0x0E284006, 165 .emif_rd_wr_exec_thresh = 0x80000405, 166 .emif_ddr_ext_phy_ctrl_1 = 0x04010040, 167 .emif_ddr_ext_phy_ctrl_2 = 0x00500050, 168 .emif_ddr_ext_phy_ctrl_3 = 0x00500050, 169 .emif_ddr_ext_phy_ctrl_4 = 0x00500050, 170 .emif_ddr_ext_phy_ctrl_5 = 0x00500050, 171 .emif_prio_class_serv_map = 0x80000001, 172 .emif_connect_id_serv_1_map = 0x80000094, 173 .emif_connect_id_serv_2_map = 0x00000000, 174 .emif_cos_config = 0x000FFFFF 175 }; 176 177 const struct ctrl_ioregs ioregs_ddr3 = { 178 .cm0ioctl = DDR3_ADDRCTRL_IOCTRL_VALUE, 179 .cm1ioctl = DDR3_ADDRCTRL_WD0_IOCTRL_VALUE, 180 .cm2ioctl = DDR3_ADDRCTRL_WD1_IOCTRL_VALUE, 181 .dt0ioctl = DDR3_DATA0_IOCTRL_VALUE, 182 .dt1ioctl = DDR3_DATA0_IOCTRL_VALUE, 183 .dt2ioctrl = DDR3_DATA0_IOCTRL_VALUE, 184 .dt3ioctrl = DDR3_DATA0_IOCTRL_VALUE, 185 .emif_sdram_config_ext = 0xc163, 186 }; 187 188 const struct emif_regs ddr3_emif_regs_400Mhz = { 189 .sdram_config = 0x638413B2, 190 .ref_ctrl = 0x00000C30, 191 .sdram_tim1 = 0xEAAAD4DB, 192 .sdram_tim2 = 0x266B7FDA, 193 .sdram_tim3 = 0x107F8678, 194 .read_idle_ctrl = 0x00050000, 195 .zq_config = 0x50074BE4, 196 .temp_alert_config = 0x0, 197 .emif_ddr_phy_ctlr_1 = 0x0E004008, 198 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 199 .emif_ddr_ext_phy_ctrl_2 = 0x00400040, 200 .emif_ddr_ext_phy_ctrl_3 = 0x00400040, 201 .emif_ddr_ext_phy_ctrl_4 = 0x00400040, 202 .emif_ddr_ext_phy_ctrl_5 = 0x00400040, 203 .emif_rd_wr_lvl_rmp_win = 0x0, 204 .emif_rd_wr_lvl_rmp_ctl = 0x0, 205 .emif_rd_wr_lvl_ctl = 0x0, 206 .emif_rd_wr_exec_thresh = 0x80000405, 207 .emif_prio_class_serv_map = 0x80000001, 208 .emif_connect_id_serv_1_map = 0x80000094, 209 .emif_connect_id_serv_2_map = 0x00000000, 210 .emif_cos_config = 0x000FFFFF 211 }; 212 213 /* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */ 214 const struct emif_regs ddr3_emif_regs_400Mhz_beta = { 215 .sdram_config = 0x638413B2, 216 .ref_ctrl = 0x00000C30, 217 .sdram_tim1 = 0xEAAAD4DB, 218 .sdram_tim2 = 0x266B7FDA, 219 .sdram_tim3 = 0x107F8678, 220 .read_idle_ctrl = 0x00050000, 221 .zq_config = 0x50074BE4, 222 .temp_alert_config = 0x0, 223 .emif_ddr_phy_ctlr_1 = 0x0E004008, 224 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 225 .emif_ddr_ext_phy_ctrl_2 = 0x00000065, 226 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 227 .emif_ddr_ext_phy_ctrl_4 = 0x000000B5, 228 .emif_ddr_ext_phy_ctrl_5 = 0x000000E5, 229 .emif_rd_wr_exec_thresh = 0x80000405, 230 .emif_prio_class_serv_map = 0x80000001, 231 .emif_connect_id_serv_1_map = 0x80000094, 232 .emif_connect_id_serv_2_map = 0x00000000, 233 .emif_cos_config = 0x000FFFFF 234 }; 235 236 /* EMIF DDR3 Configurations are different for production AM43X GP EVMs */ 237 const struct emif_regs ddr3_emif_regs_400Mhz_production = { 238 .sdram_config = 0x638413B2, 239 .ref_ctrl = 0x00000C30, 240 .sdram_tim1 = 0xEAAAD4DB, 241 .sdram_tim2 = 0x266B7FDA, 242 .sdram_tim3 = 0x107F8678, 243 .read_idle_ctrl = 0x00050000, 244 .zq_config = 0x50074BE4, 245 .temp_alert_config = 0x0, 246 .emif_ddr_phy_ctlr_1 = 0x0E004008, 247 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 248 .emif_ddr_ext_phy_ctrl_2 = 0x00000066, 249 .emif_ddr_ext_phy_ctrl_3 = 0x00000091, 250 .emif_ddr_ext_phy_ctrl_4 = 0x000000B9, 251 .emif_ddr_ext_phy_ctrl_5 = 0x000000E6, 252 .emif_rd_wr_exec_thresh = 0x80000405, 253 .emif_prio_class_serv_map = 0x80000001, 254 .emif_connect_id_serv_1_map = 0x80000094, 255 .emif_connect_id_serv_2_map = 0x00000000, 256 .emif_cos_config = 0x000FFFFF 257 }; 258 259 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = { 260 .sdram_config = 0x638413b2, 261 .sdram_config2 = 0x00000000, 262 .ref_ctrl = 0x00000c30, 263 .sdram_tim1 = 0xeaaad4db, 264 .sdram_tim2 = 0x266b7fda, 265 .sdram_tim3 = 0x107f8678, 266 .read_idle_ctrl = 0x00050000, 267 .zq_config = 0x50074be4, 268 .temp_alert_config = 0x0, 269 .emif_ddr_phy_ctlr_1 = 0x0e084008, 270 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 271 .emif_ddr_ext_phy_ctrl_2 = 0x89, 272 .emif_ddr_ext_phy_ctrl_3 = 0x90, 273 .emif_ddr_ext_phy_ctrl_4 = 0x8e, 274 .emif_ddr_ext_phy_ctrl_5 = 0x8d, 275 .emif_rd_wr_lvl_rmp_win = 0x0, 276 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 277 .emif_rd_wr_lvl_ctl = 0x00000000, 278 .emif_rd_wr_exec_thresh = 0x80000000, 279 .emif_prio_class_serv_map = 0x80000001, 280 .emif_connect_id_serv_1_map = 0x80000094, 281 .emif_connect_id_serv_2_map = 0x00000000, 282 .emif_cos_config = 0x000FFFFF 283 }; 284 285 static const struct emif_regs ddr3_idk_emif_regs_400Mhz = { 286 .sdram_config = 0x61a11b32, 287 .sdram_config2 = 0x00000000, 288 .ref_ctrl = 0x00000c30, 289 .sdram_tim1 = 0xeaaad4db, 290 .sdram_tim2 = 0x266b7fda, 291 .sdram_tim3 = 0x107f8678, 292 .read_idle_ctrl = 0x00050000, 293 .zq_config = 0x50074be4, 294 .temp_alert_config = 0x00000000, 295 .emif_ddr_phy_ctlr_1 = 0x00008009, 296 .emif_ddr_ext_phy_ctrl_1 = 0x08020080, 297 .emif_ddr_ext_phy_ctrl_2 = 0x00000040, 298 .emif_ddr_ext_phy_ctrl_3 = 0x0000003e, 299 .emif_ddr_ext_phy_ctrl_4 = 0x00000051, 300 .emif_ddr_ext_phy_ctrl_5 = 0x00000051, 301 .emif_rd_wr_lvl_rmp_win = 0x00000000, 302 .emif_rd_wr_lvl_rmp_ctl = 0x00000000, 303 .emif_rd_wr_lvl_ctl = 0x00000000, 304 .emif_rd_wr_exec_thresh = 0x00000405, 305 .emif_prio_class_serv_map = 0x00000000, 306 .emif_connect_id_serv_1_map = 0x00000000, 307 .emif_connect_id_serv_2_map = 0x00000000, 308 .emif_cos_config = 0x00ffffff 309 }; 310 311 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) 312 { 313 if (board_is_eposevm()) { 314 *regs = ext_phy_ctrl_const_base_lpddr2; 315 *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); 316 } 317 318 return; 319 } 320 321 const struct dpll_params *get_dpll_ddr_params(void) 322 { 323 int ind = get_sys_clk_index(); 324 325 if (board_is_eposevm()) 326 return &epos_evm_dpll_ddr[ind]; 327 else if (board_is_evm() || board_is_sk()) 328 return &gp_evm_dpll_ddr; 329 else if (board_is_idk()) 330 return &idk_dpll_ddr; 331 332 printf(" Board '%s' not supported\n", board_ti_get_name()); 333 return NULL; 334 } 335 336 337 /* 338 * get_opp_offset: 339 * Returns the index for safest OPP of the device to boot. 340 * max_off: Index of the MAX OPP in DEV ATTRIBUTE register. 341 * min_off: Index of the MIN OPP in DEV ATTRIBUTE register. 342 * This data is read from dev_attribute register which is e-fused. 343 * A'1' in bit indicates OPP disabled and not available, a '0' indicates 344 * OPP available. Lowest OPP starts with min_off. So returning the 345 * bit with rightmost '0'. 346 */ 347 static int get_opp_offset(int max_off, int min_off) 348 { 349 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE; 350 int opp, offset, i; 351 352 /* Bits 0:11 are defined to be the MPU_MAX_FREQ */ 353 opp = readl(&ctrl->dev_attr) & ~0xFFFFF000; 354 355 for (i = max_off; i >= min_off; i--) { 356 offset = opp & (1 << i); 357 if (!offset) 358 return i; 359 } 360 361 return min_off; 362 } 363 364 const struct dpll_params *get_dpll_mpu_params(void) 365 { 366 int opp = get_opp_offset(DEV_ATTR_MAX_OFFSET, DEV_ATTR_MIN_OFFSET); 367 u32 ind = get_sys_clk_index(); 368 369 return &dpll_mpu[ind][opp]; 370 } 371 372 const struct dpll_params *get_dpll_core_params(void) 373 { 374 int ind = get_sys_clk_index(); 375 376 return &dpll_core[ind]; 377 } 378 379 const struct dpll_params *get_dpll_per_params(void) 380 { 381 int ind = get_sys_clk_index(); 382 383 return &dpll_per[ind]; 384 } 385 386 void scale_vcores_generic(u32 m) 387 { 388 int mpu_vdd; 389 390 if (i2c_probe(TPS65218_CHIP_PM)) 391 return; 392 393 switch (m) { 394 case 1000: 395 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV; 396 break; 397 case 800: 398 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1260MV; 399 break; 400 case 720: 401 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1200MV; 402 break; 403 case 600: 404 mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV; 405 break; 406 case 300: 407 mpu_vdd = TPS65218_DCDC_VOLT_SEL_0950MV; 408 break; 409 default: 410 puts("Unknown MPU clock, not scaling\n"); 411 return; 412 } 413 414 /* Set DCDC1 (CORE) voltage to 1.1V */ 415 if (tps65218_voltage_update(TPS65218_DCDC1, 416 TPS65218_DCDC_VOLT_SEL_1100MV)) { 417 printf("%s failure\n", __func__); 418 return; 419 } 420 421 /* Set DCDC2 (MPU) voltage */ 422 if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) { 423 printf("%s failure\n", __func__); 424 return; 425 } 426 427 /* Set DCDC3 (DDR) voltage */ 428 if (tps65218_voltage_update(TPS65218_DCDC3, 429 TPS65218_DCDC3_VOLT_SEL_1350MV)) { 430 printf("%s failure\n", __func__); 431 return; 432 } 433 } 434 435 void scale_vcores_idk(u32 m) 436 { 437 int mpu_vdd; 438 439 if (i2c_probe(TPS62362_I2C_ADDR)) 440 return; 441 442 switch (m) { 443 case 1000: 444 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 445 break; 446 case 800: 447 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1260MV; 448 break; 449 case 720: 450 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1200MV; 451 break; 452 case 600: 453 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1100MV; 454 break; 455 case 300: 456 mpu_vdd = TPS62362_DCDC_VOLT_SEL_1330MV; 457 break; 458 default: 459 puts("Unknown MPU clock, not scaling\n"); 460 return; 461 } 462 463 /* Set VDD_MPU voltage */ 464 if (tps62362_voltage_update(TPS62362_SET3, mpu_vdd)) { 465 printf("%s failure\n", __func__); 466 return; 467 } 468 } 469 470 void gpi2c_init(void) 471 { 472 /* When needed to be invoked prior to BSS initialization */ 473 static bool first_time = true; 474 475 if (first_time) { 476 enable_i2c0_pin_mux(); 477 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 478 CONFIG_SYS_OMAP24_I2C_SLAVE); 479 first_time = false; 480 } 481 } 482 483 void scale_vcores(void) 484 { 485 const struct dpll_params *mpu_params; 486 487 /* Ensure I2C is initialized for PMIC configuration */ 488 gpi2c_init(); 489 490 /* Get the frequency */ 491 mpu_params = get_dpll_mpu_params(); 492 493 if (board_is_idk()) 494 scale_vcores_idk(mpu_params->m); 495 else 496 scale_vcores_generic(mpu_params->m); 497 } 498 499 void set_uart_mux_conf(void) 500 { 501 enable_uart0_pin_mux(); 502 } 503 504 void set_mux_conf_regs(void) 505 { 506 enable_board_pin_mux(); 507 } 508 509 static void enable_vtt_regulator(void) 510 { 511 u32 temp; 512 513 /* enable module */ 514 writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL); 515 516 /* enable output for GPIO5_7 */ 517 writel(GPIO_SETDATAOUT(7), 518 AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT); 519 temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 520 temp = temp & ~(GPIO_OE_ENABLE(7)); 521 writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE); 522 } 523 524 enum { 525 RTC_BOARD_EPOS = 1, 526 RTC_BOARD_EVM14, 527 RTC_BOARD_EVM12, 528 RTC_BOARD_GPEVM, 529 RTC_BOARD_SK, 530 }; 531 532 /* 533 * In the rtc_only+DRR in self-refresh boot path we have the board type info 534 * in the rtc scratch pad register hence we bypass the costly i2c reads to 535 * eeprom and directly programthe board name string 536 */ 537 void rtc_only_update_board_type(u32 btype) 538 { 539 const char *name = ""; 540 const char *rev = "1.0"; 541 542 switch (btype) { 543 case RTC_BOARD_EPOS: 544 name = "AM43EPOS"; 545 break; 546 case RTC_BOARD_EVM14: 547 name = "AM43__GP"; 548 rev = "1.4"; 549 break; 550 case RTC_BOARD_EVM12: 551 name = "AM43__GP"; 552 rev = "1.2"; 553 break; 554 case RTC_BOARD_GPEVM: 555 name = "AM43__GP"; 556 break; 557 case RTC_BOARD_SK: 558 name = "AM43__SK"; 559 break; 560 } 561 ti_i2c_eeprom_am_set(name, rev); 562 } 563 564 u32 rtc_only_get_board_type(void) 565 { 566 if (board_is_eposevm()) 567 return RTC_BOARD_EPOS; 568 else if (board_is_evm_14_or_later()) 569 return RTC_BOARD_EVM14; 570 else if (board_is_evm_12_or_later()) 571 return RTC_BOARD_EVM12; 572 else if (board_is_gpevm()) 573 return RTC_BOARD_GPEVM; 574 else if (board_is_sk()) 575 return RTC_BOARD_SK; 576 577 return 0; 578 } 579 580 void sdram_init(void) 581 { 582 /* 583 * EPOS EVM has 1GB LPDDR2 connected to EMIF. 584 * GP EMV has 1GB DDR3 connected to EMIF 585 * along with VTT regulator. 586 */ 587 if (board_is_eposevm()) { 588 config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0); 589 } else if (board_is_evm_14_or_later()) { 590 enable_vtt_regulator(); 591 config_ddr(0, &ioregs_ddr3, NULL, NULL, 592 &ddr3_emif_regs_400Mhz_production, 0); 593 } else if (board_is_evm_12_or_later()) { 594 enable_vtt_regulator(); 595 config_ddr(0, &ioregs_ddr3, NULL, NULL, 596 &ddr3_emif_regs_400Mhz_beta, 0); 597 } else if (board_is_evm()) { 598 enable_vtt_regulator(); 599 config_ddr(0, &ioregs_ddr3, NULL, NULL, 600 &ddr3_emif_regs_400Mhz, 0); 601 } else if (board_is_sk()) { 602 config_ddr(400, &ioregs_ddr3, NULL, NULL, 603 &ddr3_sk_emif_regs_400Mhz, 0); 604 } else if (board_is_idk()) { 605 config_ddr(400, &ioregs_ddr3, NULL, NULL, 606 &ddr3_idk_emif_regs_400Mhz, 0); 607 } 608 } 609 #endif 610 611 /* setup board specific PMIC */ 612 int power_init_board(void) 613 { 614 struct pmic *p; 615 616 if (board_is_idk()) { 617 power_tps62362_init(I2C_PMIC); 618 p = pmic_get("TPS62362"); 619 if (p && !pmic_probe(p)) 620 puts("PMIC: TPS62362\n"); 621 } else { 622 power_tps65218_init(I2C_PMIC); 623 p = pmic_get("TPS65218_PMIC"); 624 if (p && !pmic_probe(p)) 625 puts("PMIC: TPS65218\n"); 626 } 627 628 return 0; 629 } 630 631 int board_init(void) 632 { 633 struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER; 634 u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional, 635 modena_init0_bw_integer, modena_init0_watermark_0; 636 637 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 638 gpmc_init(); 639 640 /* 641 * Call this to initialize *ctrl again 642 */ 643 hw_data_init(); 644 645 /* Clear all important bits for DSS errata that may need to be tweaked*/ 646 mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK & 647 MREQPRIO_0_SAB_INIT0_MASK; 648 649 mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK; 650 651 modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) & 652 BW_LIMITER_BW_FRAC_MASK; 653 654 modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) & 655 BW_LIMITER_BW_INT_MASK; 656 657 modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) & 658 BW_LIMITER_BW_WATERMARK_MASK; 659 660 /* Setting MReq Priority of the DSS*/ 661 mreqprio_0 |= 0x77; 662 663 /* 664 * Set L3 Fast Configuration Register 665 * Limiting bandwith for ARM core to 700 MBPS 666 */ 667 modena_init0_bw_fractional |= 0x10; 668 modena_init0_bw_integer |= 0x3; 669 670 writel(mreqprio_0, &cdev->mreqprio_0); 671 writel(mreqprio_1, &cdev->mreqprio_1); 672 673 writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional); 674 writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer); 675 writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0); 676 677 return 0; 678 } 679 680 #ifdef CONFIG_BOARD_LATE_INIT 681 int board_late_init(void) 682 { 683 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 684 set_board_info_env(NULL); 685 686 /* 687 * Default FIT boot on HS devices. Non FIT images are not allowed 688 * on HS devices. 689 */ 690 if (get_device_type() == HS_DEVICE) 691 env_set("boot_fit", "1"); 692 #endif 693 return 0; 694 } 695 #endif 696 697 #ifdef CONFIG_USB_DWC3 698 static struct dwc3_device usb_otg_ss1 = { 699 .maximum_speed = USB_SPEED_HIGH, 700 .base = USB_OTG_SS1_BASE, 701 .tx_fifo_resize = false, 702 .index = 0, 703 }; 704 705 static struct dwc3_omap_device usb_otg_ss1_glue = { 706 .base = (void *)USB_OTG_SS1_GLUE_BASE, 707 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 708 .index = 0, 709 }; 710 711 static struct ti_usb_phy_device usb_phy1_device = { 712 .usb2_phy_power = (void *)USB2_PHY1_POWER, 713 .index = 0, 714 }; 715 716 static struct dwc3_device usb_otg_ss2 = { 717 .maximum_speed = USB_SPEED_HIGH, 718 .base = USB_OTG_SS2_BASE, 719 .tx_fifo_resize = false, 720 .index = 1, 721 }; 722 723 static struct dwc3_omap_device usb_otg_ss2_glue = { 724 .base = (void *)USB_OTG_SS2_GLUE_BASE, 725 .utmi_mode = DWC3_OMAP_UTMI_MODE_SW, 726 .index = 1, 727 }; 728 729 static struct ti_usb_phy_device usb_phy2_device = { 730 .usb2_phy_power = (void *)USB2_PHY2_POWER, 731 .index = 1, 732 }; 733 734 int usb_gadget_handle_interrupts(int index) 735 { 736 u32 status; 737 738 status = dwc3_omap_uboot_interrupt_status(index); 739 if (status) 740 dwc3_uboot_handle_interrupt(index); 741 742 return 0; 743 } 744 #endif /* CONFIG_USB_DWC3 */ 745 746 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 747 int board_usb_init(int index, enum usb_init_type init) 748 { 749 enable_usb_clocks(index); 750 #ifdef CONFIG_USB_DWC3 751 switch (index) { 752 case 0: 753 if (init == USB_INIT_DEVICE) { 754 usb_otg_ss1.dr_mode = USB_DR_MODE_PERIPHERAL; 755 usb_otg_ss1_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 756 dwc3_omap_uboot_init(&usb_otg_ss1_glue); 757 ti_usb_phy_uboot_init(&usb_phy1_device); 758 dwc3_uboot_init(&usb_otg_ss1); 759 } 760 break; 761 case 1: 762 if (init == USB_INIT_DEVICE) { 763 usb_otg_ss2.dr_mode = USB_DR_MODE_PERIPHERAL; 764 usb_otg_ss2_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID; 765 ti_usb_phy_uboot_init(&usb_phy2_device); 766 dwc3_omap_uboot_init(&usb_otg_ss2_glue); 767 dwc3_uboot_init(&usb_otg_ss2); 768 } 769 break; 770 default: 771 printf("Invalid Controller Index\n"); 772 } 773 #endif 774 775 return 0; 776 } 777 778 int board_usb_cleanup(int index, enum usb_init_type init) 779 { 780 #ifdef CONFIG_USB_DWC3 781 switch (index) { 782 case 0: 783 case 1: 784 if (init == USB_INIT_DEVICE) { 785 ti_usb_phy_uboot_exit(index); 786 dwc3_uboot_exit(index); 787 dwc3_omap_uboot_exit(index); 788 } 789 break; 790 default: 791 printf("Invalid Controller Index\n"); 792 } 793 #endif 794 disable_usb_clocks(index); 795 796 return 0; 797 } 798 #endif /* defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) */ 799 800 #ifdef CONFIG_DRIVER_TI_CPSW 801 802 static void cpsw_control(int enabled) 803 { 804 /* Additional controls can be added here */ 805 return; 806 } 807 808 static struct cpsw_slave_data cpsw_slaves[] = { 809 { 810 .slave_reg_ofs = 0x208, 811 .sliver_reg_ofs = 0xd80, 812 .phy_addr = 16, 813 }, 814 { 815 .slave_reg_ofs = 0x308, 816 .sliver_reg_ofs = 0xdc0, 817 .phy_addr = 1, 818 }, 819 }; 820 821 static struct cpsw_platform_data cpsw_data = { 822 .mdio_base = CPSW_MDIO_BASE, 823 .cpsw_base = CPSW_BASE, 824 .mdio_div = 0xff, 825 .channels = 8, 826 .cpdma_reg_ofs = 0x800, 827 .slaves = 1, 828 .slave_data = cpsw_slaves, 829 .ale_reg_ofs = 0xd00, 830 .ale_entries = 1024, 831 .host_port_reg_ofs = 0x108, 832 .hw_stats_reg_ofs = 0x900, 833 .bd_ram_ofs = 0x2000, 834 .mac_control = (1 << 5), 835 .control = cpsw_control, 836 .host_port_num = 0, 837 .version = CPSW_CTRL_VERSION_2, 838 }; 839 840 int board_eth_init(bd_t *bis) 841 { 842 int rv; 843 uint8_t mac_addr[6]; 844 uint32_t mac_hi, mac_lo; 845 846 /* try reading mac address from efuse */ 847 mac_lo = readl(&cdev->macid0l); 848 mac_hi = readl(&cdev->macid0h); 849 mac_addr[0] = mac_hi & 0xFF; 850 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 851 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 852 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 853 mac_addr[4] = mac_lo & 0xFF; 854 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 855 856 if (!env_get("ethaddr")) { 857 puts("<ethaddr> not set. Validating first E-fuse MAC\n"); 858 if (is_valid_ethaddr(mac_addr)) 859 eth_env_set_enetaddr("ethaddr", mac_addr); 860 } 861 862 mac_lo = readl(&cdev->macid1l); 863 mac_hi = readl(&cdev->macid1h); 864 mac_addr[0] = mac_hi & 0xFF; 865 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 866 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 867 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 868 mac_addr[4] = mac_lo & 0xFF; 869 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 870 871 if (!env_get("eth1addr")) { 872 if (is_valid_ethaddr(mac_addr)) 873 eth_env_set_enetaddr("eth1addr", mac_addr); 874 } 875 876 if (board_is_eposevm()) { 877 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 878 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 879 cpsw_slaves[0].phy_addr = 16; 880 } else if (board_is_sk()) { 881 writel(RGMII_MODE_ENABLE, &cdev->miisel); 882 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 883 cpsw_slaves[0].phy_addr = 4; 884 cpsw_slaves[1].phy_addr = 5; 885 } else if (board_is_idk()) { 886 writel(RGMII_MODE_ENABLE, &cdev->miisel); 887 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 888 cpsw_slaves[0].phy_addr = 0; 889 } else { 890 writel(RGMII_MODE_ENABLE, &cdev->miisel); 891 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; 892 cpsw_slaves[0].phy_addr = 0; 893 } 894 895 rv = cpsw_register(&cpsw_data); 896 if (rv < 0) 897 printf("Error %d registering CPSW switch\n", rv); 898 899 return rv; 900 } 901 #endif 902 903 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 904 int ft_board_setup(void *blob, bd_t *bd) 905 { 906 ft_cpu_setup(blob, bd); 907 908 return 0; 909 } 910 #endif 911 912 #if defined(CONFIG_SPL_LOAD_FIT) || defined(CONFIG_DTB_RESELECT) 913 int board_fit_config_name_match(const char *name) 914 { 915 bool eeprom_read = board_ti_was_eeprom_read(); 916 917 if (!strcmp(name, "am4372-generic") && !eeprom_read) 918 return 0; 919 else if (board_is_evm() && !strcmp(name, "am437x-gp-evm")) 920 return 0; 921 else if (board_is_sk() && !strcmp(name, "am437x-sk-evm")) 922 return 0; 923 else if (board_is_eposevm() && !strcmp(name, "am43x-epos-evm")) 924 return 0; 925 else if (board_is_idk() && !strcmp(name, "am437x-idk-evm")) 926 return 0; 927 else 928 return -1; 929 } 930 #endif 931 932 #ifdef CONFIG_DTB_RESELECT 933 int embedded_dtb_select(void) 934 { 935 do_board_detect(); 936 fdtdec_setup(); 937 938 return 0; 939 } 940 #endif 941 942 #ifdef CONFIG_TI_SECURE_DEVICE 943 void board_fit_image_post_process(void **p_image, size_t *p_size) 944 { 945 secure_boot_verify_image(p_image, p_size); 946 } 947 948 void board_tee_image_process(ulong tee_image, size_t tee_size) 949 { 950 secure_tee_install((u32)tee_image); 951 } 952 953 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process); 954 #endif 955