1 /* 2 * board.c 3 * 4 * Board functions for TI AM335X based boards 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 #include <dm.h> 13 #include <errno.h> 14 #include <spl.h> 15 #include <serial.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/hardware.h> 18 #include <asm/arch/omap.h> 19 #include <asm/arch/ddr_defs.h> 20 #include <asm/arch/clock.h> 21 #include <asm/arch/clk_synthesizer.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/sys_proto.h> 25 #include <asm/arch/mem.h> 26 #include <asm/io.h> 27 #include <asm/emif.h> 28 #include <asm/gpio.h> 29 #include <asm/omap_common.h> 30 #include <asm/omap_sec_common.h> 31 #include <asm/omap_mmc.h> 32 #include <i2c.h> 33 #include <miiphy.h> 34 #include <cpsw.h> 35 #include <power/tps65217.h> 36 #include <power/tps65910.h> 37 #include <environment.h> 38 #include <watchdog.h> 39 #include <environment.h> 40 #include "../common/board_detect.h" 41 #include "board.h" 42 43 DECLARE_GLOBAL_DATA_PTR; 44 45 /* GPIO that controls power to DDR on EVM-SK */ 46 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio)) 47 #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7) 48 #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18) 49 #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4) 50 #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10) 51 #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7) 52 #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5) 53 #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11) 54 #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26) 55 56 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 57 58 #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT) 59 #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT) 60 61 #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1) 62 #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1) 63 64 #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024) 65 #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024) 66 67 /* 68 * Read header information from EEPROM into global structure. 69 */ 70 #ifdef CONFIG_TI_I2C_BOARD_DETECT 71 void do_board_detect(void) 72 { 73 enable_i2c0_pin_mux(); 74 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 75 76 if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS, 77 CONFIG_EEPROM_CHIP_ADDRESS)) 78 printf("ti_i2c_eeprom_init failed\n"); 79 } 80 #endif 81 82 #ifndef CONFIG_DM_SERIAL 83 struct serial_device *default_serial_console(void) 84 { 85 if (board_is_icev2()) 86 return &eserial4_device; 87 else 88 return &eserial1_device; 89 } 90 #endif 91 92 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 93 static const struct ddr_data ddr2_data = { 94 .datardsratio0 = MT47H128M16RT25E_RD_DQS, 95 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE, 96 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA, 97 }; 98 99 static const struct cmd_control ddr2_cmd_ctrl_data = { 100 .cmd0csratio = MT47H128M16RT25E_RATIO, 101 102 .cmd1csratio = MT47H128M16RT25E_RATIO, 103 104 .cmd2csratio = MT47H128M16RT25E_RATIO, 105 }; 106 107 static const struct emif_regs ddr2_emif_reg_data = { 108 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 109 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 110 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 111 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 112 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 113 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 114 }; 115 116 static const struct emif_regs ddr2_evm_emif_reg_data = { 117 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 118 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 119 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 120 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 121 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 122 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, 123 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 124 }; 125 126 static const struct ddr_data ddr3_data = { 127 .datardsratio0 = MT41J128MJT125_RD_DQS, 128 .datawdsratio0 = MT41J128MJT125_WR_DQS, 129 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 130 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 131 }; 132 133 static const struct ddr_data ddr3_beagleblack_data = { 134 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 135 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 136 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 137 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 138 }; 139 140 static const struct ddr_data ddr3_evm_data = { 141 .datardsratio0 = MT41J512M8RH125_RD_DQS, 142 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 143 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 144 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 145 }; 146 147 static const struct ddr_data ddr3_icev2_data = { 148 .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz, 149 .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz, 150 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz, 151 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz, 152 }; 153 154 static const struct cmd_control ddr3_cmd_ctrl_data = { 155 .cmd0csratio = MT41J128MJT125_RATIO, 156 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 157 158 .cmd1csratio = MT41J128MJT125_RATIO, 159 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 160 161 .cmd2csratio = MT41J128MJT125_RATIO, 162 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 163 }; 164 165 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 166 .cmd0csratio = MT41K256M16HA125E_RATIO, 167 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 168 169 .cmd1csratio = MT41K256M16HA125E_RATIO, 170 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 171 172 .cmd2csratio = MT41K256M16HA125E_RATIO, 173 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 174 }; 175 176 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 177 .cmd0csratio = MT41J512M8RH125_RATIO, 178 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 179 180 .cmd1csratio = MT41J512M8RH125_RATIO, 181 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 182 183 .cmd2csratio = MT41J512M8RH125_RATIO, 184 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 185 }; 186 187 static const struct cmd_control ddr3_icev2_cmd_ctrl_data = { 188 .cmd0csratio = MT41J128MJT125_RATIO_400MHz, 189 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 190 191 .cmd1csratio = MT41J128MJT125_RATIO_400MHz, 192 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 193 194 .cmd2csratio = MT41J128MJT125_RATIO_400MHz, 195 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz, 196 }; 197 198 static struct emif_regs ddr3_emif_reg_data = { 199 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 200 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 201 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 202 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 203 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 204 .zq_config = MT41J128MJT125_ZQ_CFG, 205 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 206 PHY_EN_DYN_PWRDN, 207 }; 208 209 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 210 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 211 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 212 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 213 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 214 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 215 .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK, 216 .zq_config = MT41K256M16HA125E_ZQ_CFG, 217 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 218 }; 219 220 static struct emif_regs ddr3_evm_emif_reg_data = { 221 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 222 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 223 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 224 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 225 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 226 .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM, 227 .zq_config = MT41J512M8RH125_ZQ_CFG, 228 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 229 PHY_EN_DYN_PWRDN, 230 }; 231 232 static struct emif_regs ddr3_icev2_emif_reg_data = { 233 .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz, 234 .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz, 235 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz, 236 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz, 237 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz, 238 .zq_config = MT41J128MJT125_ZQ_CFG_400MHz, 239 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz | 240 PHY_EN_DYN_PWRDN, 241 }; 242 243 #ifdef CONFIG_SPL_OS_BOOT 244 int spl_start_uboot(void) 245 { 246 #ifdef CONFIG_SPL_SERIAL_SUPPORT 247 /* break into full u-boot on 'c' */ 248 if (serial_tstc() && serial_getc() == 'c') 249 return 1; 250 #endif 251 252 #ifdef CONFIG_SPL_ENV_SUPPORT 253 env_init(); 254 env_load(); 255 if (env_get_yesno("boot_os") != 1) 256 return 1; 257 #endif 258 259 return 0; 260 } 261 #endif 262 263 const struct dpll_params *get_dpll_ddr_params(void) 264 { 265 int ind = get_sys_clk_index(); 266 267 if (board_is_evm_sk()) 268 return &dpll_ddr3_303MHz[ind]; 269 else if (board_is_pb() || board_is_bone_lt() || board_is_icev2()) 270 return &dpll_ddr3_400MHz[ind]; 271 else if (board_is_evm_15_or_later()) 272 return &dpll_ddr3_303MHz[ind]; 273 else 274 return &dpll_ddr2_266MHz[ind]; 275 } 276 277 static u8 bone_not_connected_to_ac_power(void) 278 { 279 if (board_is_bone()) { 280 uchar pmic_status_reg; 281 if (tps65217_reg_read(TPS65217_STATUS, 282 &pmic_status_reg)) 283 return 1; 284 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 285 puts("No AC power, switching to default OPP\n"); 286 return 1; 287 } 288 } 289 return 0; 290 } 291 292 const struct dpll_params *get_dpll_mpu_params(void) 293 { 294 int ind = get_sys_clk_index(); 295 int freq = am335x_get_efuse_mpu_max_freq(cdev); 296 297 if (bone_not_connected_to_ac_power()) 298 freq = MPUPLL_M_600; 299 300 if (board_is_pb() || board_is_bone_lt()) 301 freq = MPUPLL_M_1000; 302 303 switch (freq) { 304 case MPUPLL_M_1000: 305 return &dpll_mpu_opp[ind][5]; 306 case MPUPLL_M_800: 307 return &dpll_mpu_opp[ind][4]; 308 case MPUPLL_M_720: 309 return &dpll_mpu_opp[ind][3]; 310 case MPUPLL_M_600: 311 return &dpll_mpu_opp[ind][2]; 312 case MPUPLL_M_500: 313 return &dpll_mpu_opp100; 314 case MPUPLL_M_300: 315 return &dpll_mpu_opp[ind][0]; 316 } 317 318 return &dpll_mpu_opp[ind][0]; 319 } 320 321 static void scale_vcores_bone(int freq) 322 { 323 int usb_cur_lim, mpu_vdd; 324 325 /* 326 * Only perform PMIC configurations if board rev > A1 327 * on Beaglebone White 328 */ 329 if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4)) 330 return; 331 332 if (i2c_probe(TPS65217_CHIP_PM)) 333 return; 334 335 /* 336 * On Beaglebone White we need to ensure we have AC power 337 * before increasing the frequency. 338 */ 339 if (bone_not_connected_to_ac_power()) 340 freq = MPUPLL_M_600; 341 342 /* 343 * Override what we have detected since we know if we have 344 * a Beaglebone Black it supports 1GHz. 345 */ 346 if (board_is_pb() || board_is_bone_lt()) 347 freq = MPUPLL_M_1000; 348 349 switch (freq) { 350 case MPUPLL_M_1000: 351 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 352 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 353 break; 354 case MPUPLL_M_800: 355 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 356 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 357 break; 358 case MPUPLL_M_720: 359 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; 360 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 361 break; 362 case MPUPLL_M_600: 363 case MPUPLL_M_500: 364 case MPUPLL_M_300: 365 default: 366 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; 367 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 368 break; 369 } 370 371 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 372 TPS65217_POWER_PATH, 373 usb_cur_lim, 374 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 375 puts("tps65217_reg_write failure\n"); 376 377 /* Set DCDC3 (CORE) voltage to 1.10V */ 378 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 379 TPS65217_DCDC_VOLT_SEL_1100MV)) { 380 puts("tps65217_voltage_update failure\n"); 381 return; 382 } 383 384 /* Set DCDC2 (MPU) voltage */ 385 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 386 puts("tps65217_voltage_update failure\n"); 387 return; 388 } 389 390 /* 391 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 392 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black. 393 */ 394 if (board_is_bone()) { 395 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 396 TPS65217_DEFLS1, 397 TPS65217_LDO_VOLTAGE_OUT_3_3, 398 TPS65217_LDO_MASK)) 399 puts("tps65217_reg_write failure\n"); 400 } else { 401 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 402 TPS65217_DEFLS1, 403 TPS65217_LDO_VOLTAGE_OUT_1_8, 404 TPS65217_LDO_MASK)) 405 puts("tps65217_reg_write failure\n"); 406 } 407 408 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 409 TPS65217_DEFLS2, 410 TPS65217_LDO_VOLTAGE_OUT_3_3, 411 TPS65217_LDO_MASK)) 412 puts("tps65217_reg_write failure\n"); 413 } 414 415 void scale_vcores_generic(int freq) 416 { 417 int sil_rev, mpu_vdd; 418 419 /* 420 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 421 * MPU frequencies we support we use a CORE voltage of 422 * 1.10V. For MPU voltage we need to switch based on 423 * the frequency we are running at. 424 */ 425 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 426 return; 427 428 /* 429 * Depending on MPU clock and PG we will need a different 430 * VDD to drive at that speed. 431 */ 432 sil_rev = readl(&cdev->deviceid) >> 28; 433 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); 434 435 /* Tell the TPS65910 to use i2c */ 436 tps65910_set_i2c_control(); 437 438 /* First update MPU voltage. */ 439 if (tps65910_voltage_update(MPU, mpu_vdd)) 440 return; 441 442 /* Second, update the CORE voltage. */ 443 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0)) 444 return; 445 446 } 447 448 void gpi2c_init(void) 449 { 450 /* When needed to be invoked prior to BSS initialization */ 451 static bool first_time = true; 452 453 if (first_time) { 454 enable_i2c0_pin_mux(); 455 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, 456 CONFIG_SYS_OMAP24_I2C_SLAVE); 457 first_time = false; 458 } 459 } 460 461 void scale_vcores(void) 462 { 463 int freq; 464 465 gpi2c_init(); 466 freq = am335x_get_efuse_mpu_max_freq(cdev); 467 468 if (board_is_beaglebonex()) 469 scale_vcores_bone(freq); 470 else 471 scale_vcores_generic(freq); 472 } 473 474 void set_uart_mux_conf(void) 475 { 476 #if CONFIG_CONS_INDEX == 1 477 enable_uart0_pin_mux(); 478 #elif CONFIG_CONS_INDEX == 2 479 enable_uart1_pin_mux(); 480 #elif CONFIG_CONS_INDEX == 3 481 enable_uart2_pin_mux(); 482 #elif CONFIG_CONS_INDEX == 4 483 enable_uart3_pin_mux(); 484 #elif CONFIG_CONS_INDEX == 5 485 enable_uart4_pin_mux(); 486 #elif CONFIG_CONS_INDEX == 6 487 enable_uart5_pin_mux(); 488 #endif 489 } 490 491 void set_mux_conf_regs(void) 492 { 493 enable_board_pin_mux(); 494 } 495 496 const struct ctrl_ioregs ioregs_evmsk = { 497 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 498 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 499 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 500 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 501 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 502 }; 503 504 const struct ctrl_ioregs ioregs_bonelt = { 505 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 506 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 507 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 508 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 509 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 510 }; 511 512 const struct ctrl_ioregs ioregs_evm15 = { 513 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 514 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 515 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, 516 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 517 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 518 }; 519 520 const struct ctrl_ioregs ioregs = { 521 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 522 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 523 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 524 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 525 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 526 }; 527 528 void sdram_init(void) 529 { 530 if (board_is_evm_sk()) { 531 /* 532 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 533 * This is safe enough to do on older revs. 534 */ 535 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 536 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 537 } 538 539 if (board_is_icev2()) { 540 gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en"); 541 gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1); 542 } 543 544 if (board_is_evm_sk()) 545 config_ddr(303, &ioregs_evmsk, &ddr3_data, 546 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 547 else if (board_is_pb() || board_is_bone_lt()) 548 config_ddr(400, &ioregs_bonelt, 549 &ddr3_beagleblack_data, 550 &ddr3_beagleblack_cmd_ctrl_data, 551 &ddr3_beagleblack_emif_reg_data, 0); 552 else if (board_is_evm_15_or_later()) 553 config_ddr(303, &ioregs_evm15, &ddr3_evm_data, 554 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 555 else if (board_is_icev2()) 556 config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, 557 &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 558 0); 559 else if (board_is_gp_evm()) 560 config_ddr(266, &ioregs, &ddr2_data, 561 &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0); 562 else 563 config_ddr(266, &ioregs, &ddr2_data, 564 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 565 } 566 #endif 567 568 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ 569 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))) 570 static void request_and_set_gpio(int gpio, char *name, int val) 571 { 572 int ret; 573 574 ret = gpio_request(gpio, name); 575 if (ret < 0) { 576 printf("%s: Unable to request %s\n", __func__, name); 577 return; 578 } 579 580 ret = gpio_direction_output(gpio, 0); 581 if (ret < 0) { 582 printf("%s: Unable to set %s as output\n", __func__, name); 583 goto err_free_gpio; 584 } 585 586 gpio_set_value(gpio, val); 587 588 return; 589 590 err_free_gpio: 591 gpio_free(gpio); 592 } 593 594 #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1); 595 #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0); 596 597 /** 598 * RMII mode on ICEv2 board needs 50MHz clock. Given the clock 599 * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle 600 * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to 601 * give 50MHz output for Eth0 and 1. 602 */ 603 static struct clk_synth cdce913_data = { 604 .id = 0x81, 605 .capacitor = 0x90, 606 .mux = 0x6d, 607 .pdiv2 = 0x2, 608 .pdiv3 = 0x2, 609 }; 610 #endif 611 612 /* 613 * Basic board specific setup. Pinmux has been handled already. 614 */ 615 int board_init(void) 616 { 617 #if defined(CONFIG_HW_WATCHDOG) 618 hw_watchdog_init(); 619 #endif 620 621 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 622 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 623 gpmc_init(); 624 #endif 625 626 #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \ 627 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))) 628 if (board_is_icev2()) { 629 int rv; 630 u32 reg; 631 632 REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL); 633 /* Make J19 status available on GPIO1_26 */ 634 REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL); 635 636 REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL); 637 /* 638 * Both ports can be set as RMII-CPSW or MII-PRU-ETH using 639 * jumpers near the port. Read the jumper value and set 640 * the pinmux, external mux and PHY clock accordingly. 641 * As jumper line is overridden by PHY RX_DV pin immediately 642 * after bootstrap (power-up/reset), we need to sample 643 * it during PHY reset using GPIO rising edge detection. 644 */ 645 REQUEST_AND_SET_GPIO(GPIO_PHY_RESET); 646 /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */ 647 reg = readl(GPIO0_RISINGDETECT) | BIT(11); 648 writel(reg, GPIO0_RISINGDETECT); 649 reg = readl(GPIO1_RISINGDETECT) | BIT(26); 650 writel(reg, GPIO1_RISINGDETECT); 651 /* Reset PHYs to capture the Jumper setting */ 652 gpio_set_value(GPIO_PHY_RESET, 0); 653 udelay(2); /* PHY datasheet states 1uS min. */ 654 gpio_set_value(GPIO_PHY_RESET, 1); 655 656 reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11); 657 if (reg) { 658 writel(reg, GPIO0_IRQSTATUS1); /* clear irq */ 659 /* RMII mode */ 660 printf("ETH0, CPSW\n"); 661 } else { 662 /* MII mode */ 663 printf("ETH0, PRU\n"); 664 cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */ 665 } 666 667 reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26); 668 if (reg) { 669 writel(reg, GPIO1_IRQSTATUS1); /* clear irq */ 670 /* RMII mode */ 671 printf("ETH1, CPSW\n"); 672 gpio_set_value(GPIO_MUX_MII_CTRL, 1); 673 } else { 674 /* MII mode */ 675 printf("ETH1, PRU\n"); 676 cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */ 677 } 678 679 /* disable rising edge IRQs */ 680 reg = readl(GPIO0_RISINGDETECT) & ~BIT(11); 681 writel(reg, GPIO0_RISINGDETECT); 682 reg = readl(GPIO1_RISINGDETECT) & ~BIT(26); 683 writel(reg, GPIO1_RISINGDETECT); 684 685 rv = setup_clock_synthesizer(&cdce913_data); 686 if (rv) { 687 printf("Clock synthesizer setup failed %d\n", rv); 688 return rv; 689 } 690 691 /* reset PHYs */ 692 gpio_set_value(GPIO_PHY_RESET, 0); 693 udelay(2); /* PHY datasheet states 1uS min. */ 694 gpio_set_value(GPIO_PHY_RESET, 1); 695 } 696 #endif 697 698 return 0; 699 } 700 701 #ifdef CONFIG_BOARD_LATE_INIT 702 int board_late_init(void) 703 { 704 #if !defined(CONFIG_SPL_BUILD) 705 uint8_t mac_addr[6]; 706 uint32_t mac_hi, mac_lo; 707 #endif 708 709 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 710 char *name = NULL; 711 712 if (board_is_bone_lt()) { 713 /* BeagleBoard.org BeagleBone Black Wireless: */ 714 if (!strncmp(board_ti_get_rev(), "BWA", 3)) { 715 name = "BBBW"; 716 } 717 /* SeeedStudio BeagleBone Green Wireless */ 718 if (!strncmp(board_ti_get_rev(), "GW1", 3)) { 719 name = "BBGW"; 720 } 721 /* BeagleBoard.org BeagleBone Blue */ 722 if (!strncmp(board_ti_get_rev(), "BLA", 3)) { 723 name = "BBBL"; 724 } 725 } 726 727 if (board_is_bbg1()) 728 name = "BBG1"; 729 set_board_info_env(name); 730 731 /* 732 * Default FIT boot on HS devices. Non FIT images are not allowed 733 * on HS devices. 734 */ 735 if (get_device_type() == HS_DEVICE) 736 env_set("boot_fit", "1"); 737 #endif 738 739 #if !defined(CONFIG_SPL_BUILD) 740 /* try reading mac address from efuse */ 741 mac_lo = readl(&cdev->macid0l); 742 mac_hi = readl(&cdev->macid0h); 743 mac_addr[0] = mac_hi & 0xFF; 744 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 745 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 746 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 747 mac_addr[4] = mac_lo & 0xFF; 748 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 749 750 if (!env_get("ethaddr")) { 751 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 752 753 if (is_valid_ethaddr(mac_addr)) 754 eth_env_set_enetaddr("ethaddr", mac_addr); 755 } 756 757 mac_lo = readl(&cdev->macid1l); 758 mac_hi = readl(&cdev->macid1h); 759 mac_addr[0] = mac_hi & 0xFF; 760 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 761 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 762 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 763 mac_addr[4] = mac_lo & 0xFF; 764 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 765 766 if (!env_get("eth1addr")) { 767 if (is_valid_ethaddr(mac_addr)) 768 eth_env_set_enetaddr("eth1addr", mac_addr); 769 } 770 #endif 771 772 if (!env_get("serial#")) { 773 char *board_serial = env_get("board_serial"); 774 char *ethaddr = env_get("ethaddr"); 775 776 if (!board_serial || !strncmp(board_serial, "unknown", 7)) 777 env_set("serial#", ethaddr); 778 else 779 env_set("serial#", board_serial); 780 } 781 782 return 0; 783 } 784 #endif 785 786 #ifndef CONFIG_DM_ETH 787 788 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 789 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 790 static void cpsw_control(int enabled) 791 { 792 /* VTP can be added here */ 793 794 return; 795 } 796 797 static struct cpsw_slave_data cpsw_slaves[] = { 798 { 799 .slave_reg_ofs = 0x208, 800 .sliver_reg_ofs = 0xd80, 801 .phy_addr = 0, 802 }, 803 { 804 .slave_reg_ofs = 0x308, 805 .sliver_reg_ofs = 0xdc0, 806 .phy_addr = 1, 807 }, 808 }; 809 810 static struct cpsw_platform_data cpsw_data = { 811 .mdio_base = CPSW_MDIO_BASE, 812 .cpsw_base = CPSW_BASE, 813 .mdio_div = 0xff, 814 .channels = 8, 815 .cpdma_reg_ofs = 0x800, 816 .slaves = 1, 817 .slave_data = cpsw_slaves, 818 .ale_reg_ofs = 0xd00, 819 .ale_entries = 1024, 820 .host_port_reg_ofs = 0x108, 821 .hw_stats_reg_ofs = 0x900, 822 .bd_ram_ofs = 0x2000, 823 .mac_control = (1 << 5), 824 .control = cpsw_control, 825 .host_port_num = 0, 826 .version = CPSW_CTRL_VERSION_2, 827 }; 828 #endif 829 830 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\ 831 defined(CONFIG_SPL_BUILD)) || \ 832 ((defined(CONFIG_DRIVER_TI_CPSW) || \ 833 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ 834 !defined(CONFIG_SPL_BUILD)) 835 836 /* 837 * This function will: 838 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr 839 * in the environment 840 * Perform fixups to the PHY present on certain boards. We only need this 841 * function in: 842 * - SPL with either CPSW or USB ethernet support 843 * - Full U-Boot, with either CPSW or USB ethernet 844 * Build in only these cases to avoid warnings about unused variables 845 * when we build an SPL that has neither option but full U-Boot will. 846 */ 847 int board_eth_init(bd_t *bis) 848 { 849 int rv, n = 0; 850 #if defined(CONFIG_USB_ETHER) && \ 851 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) 852 uint8_t mac_addr[6]; 853 uint32_t mac_hi, mac_lo; 854 855 /* 856 * use efuse mac address for USB ethernet as we know that 857 * both CPSW and USB ethernet will never be active at the same time 858 */ 859 mac_lo = readl(&cdev->macid0l); 860 mac_hi = readl(&cdev->macid0h); 861 mac_addr[0] = mac_hi & 0xFF; 862 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 863 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 864 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 865 mac_addr[4] = mac_lo & 0xFF; 866 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 867 #endif 868 869 870 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 871 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 872 873 #ifdef CONFIG_DRIVER_TI_CPSW 874 if (board_is_bone() || board_is_bone_lt() || 875 board_is_idk()) { 876 writel(MII_MODE_ENABLE, &cdev->miisel); 877 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 878 PHY_INTERFACE_MODE_MII; 879 } else if (board_is_icev2()) { 880 writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); 881 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; 882 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII; 883 cpsw_slaves[0].phy_addr = 1; 884 cpsw_slaves[1].phy_addr = 3; 885 } else { 886 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 887 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 888 PHY_INTERFACE_MODE_RGMII; 889 } 890 891 rv = cpsw_register(&cpsw_data); 892 if (rv < 0) 893 printf("Error %d registering CPSW switch\n", rv); 894 else 895 n += rv; 896 #endif 897 898 /* 899 * 900 * CPSW RGMII Internal Delay Mode is not supported in all PVT 901 * operating points. So we must set the TX clock delay feature 902 * in the AR8051 PHY. Since we only support a single ethernet 903 * device in U-Boot, we only do this for the first instance. 904 */ 905 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 906 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 907 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 908 #define AR8051_RGMII_TX_CLK_DLY 0x100 909 910 if (board_is_evm_sk() || board_is_gp_evm()) { 911 const char *devname; 912 devname = miiphy_get_current_dev(); 913 914 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 915 AR8051_DEBUG_RGMII_CLK_DLY_REG); 916 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 917 AR8051_RGMII_TX_CLK_DLY); 918 } 919 #endif 920 #if defined(CONFIG_USB_ETHER) && \ 921 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) 922 if (is_valid_ethaddr(mac_addr)) 923 eth_env_set_enetaddr("usbnet_devaddr", mac_addr); 924 925 rv = usb_eth_initialize(bis); 926 if (rv < 0) 927 printf("Error %d registering USB_ETHER\n", rv); 928 else 929 n += rv; 930 #endif 931 return n; 932 } 933 #endif 934 935 #endif /* CONFIG_DM_ETH */ 936 937 #ifdef CONFIG_SPL_LOAD_FIT 938 int board_fit_config_name_match(const char *name) 939 { 940 if (board_is_gp_evm() && !strcmp(name, "am335x-evm")) 941 return 0; 942 else if (board_is_bone() && !strcmp(name, "am335x-bone")) 943 return 0; 944 else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack")) 945 return 0; 946 else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle")) 947 return 0; 948 else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk")) 949 return 0; 950 else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen")) 951 return 0; 952 else if (board_is_icev2() && !strcmp(name, "am335x-icev2")) 953 return 0; 954 else 955 return -1; 956 } 957 #endif 958 959 #ifdef CONFIG_TI_SECURE_DEVICE 960 void board_fit_image_post_process(void **p_image, size_t *p_size) 961 { 962 secure_boot_verify_image(p_image, p_size); 963 } 964 #endif 965 966 #if !CONFIG_IS_ENABLED(OF_CONTROL) 967 static const struct omap_hsmmc_plat am335x_mmc0_platdata = { 968 .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE, 969 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT, 970 .cfg.f_min = 400000, 971 .cfg.f_max = 52000000, 972 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, 973 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 974 }; 975 976 U_BOOT_DEVICE(am335x_mmc0) = { 977 .name = "omap_hsmmc", 978 .platdata = &am335x_mmc0_platdata, 979 }; 980 981 static const struct omap_hsmmc_plat am335x_mmc1_platdata = { 982 .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE, 983 .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT, 984 .cfg.f_min = 400000, 985 .cfg.f_max = 52000000, 986 .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195, 987 .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, 988 }; 989 990 U_BOOT_DEVICE(am335x_mmc1) = { 991 .name = "omap_hsmmc", 992 .platdata = &am335x_mmc1_platdata, 993 }; 994 #endif 995