1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2aea02abeSStefan Roese /* 3aea02abeSStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 4aea02abeSStefan Roese */ 5aea02abeSStefan Roese 6aea02abeSStefan Roese /* Base addresses for the SPI direct access mode */ 7aea02abeSStefan Roese #define SPI_BUS0_DEV1_BASE 0xe0000000 8aea02abeSStefan Roese #define SPI_BUS0_DEV1_SIZE (1 << 20) 9aea02abeSStefan Roese #define SPI_BUS1_DEV2_BASE (SPI_BUS0_DEV1_BASE + SPI_BUS0_DEV1_SIZE) 10aea02abeSStefan Roese 11aea02abeSStefan Roese void board_fpga_add(void); 12