1 /* 2 * (C) Copyright 2016 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <spl.h> 12 #include <asm/io.h> 13 #include <asm/armv7m.h> 14 #include <asm/arch/stm32.h> 15 #include <asm/arch/gpio.h> 16 #include <asm/arch/fmc.h> 17 #include <asm/arch/stm32_periph.h> 18 #include <asm/arch/stm32_defs.h> 19 #include <asm/arch/syscfg.h> 20 #include <asm/gpio.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int get_memory_base_size(fdt_addr_t *mr_base, fdt_addr_t *mr_size) 25 { 26 int mr_node; 27 28 mr_node = fdt_path_offset(gd->fdt_blob, "/memory"); 29 if (mr_node < 0) 30 return mr_node; 31 *mr_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, mr_node, 32 "reg", 0, mr_size, false); 33 debug("mr_base = %lx, mr_size= %lx\n", *mr_base, *mr_size); 34 35 return 0; 36 } 37 int dram_init(void) 38 { 39 int rv; 40 fdt_addr_t mr_base, mr_size; 41 42 #ifndef CONFIG_SUPPORT_SPL 43 struct udevice *dev; 44 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 45 if (rv) { 46 debug("DRAM init failed: %d\n", rv); 47 return rv; 48 } 49 50 #endif 51 rv = get_memory_base_size(&mr_base, &mr_size); 52 if (rv) 53 return rv; 54 gd->ram_size = mr_size; 55 gd->ram_top = mr_base; 56 57 return rv; 58 } 59 60 int dram_init_banksize(void) 61 { 62 fdt_addr_t mr_base, mr_size; 63 get_memory_base_size(&mr_base, &mr_size); 64 /* 65 * Fill in global info with description of SRAM configuration 66 */ 67 gd->bd->bi_dram[0].start = mr_base; 68 gd->bd->bi_dram[0].size = mr_size; 69 70 return 0; 71 } 72 73 #ifdef CONFIG_ETH_DESIGNWARE 74 static int stmmac_setup(void) 75 { 76 clock_setup(SYSCFG_CLOCK_CFG); 77 /* Set >RMII mode */ 78 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; 79 clock_setup(STMMAC_CLOCK_CFG); 80 81 return 0; 82 } 83 84 int board_early_init_f(void) 85 { 86 stmmac_setup(); 87 88 return 0; 89 } 90 #endif 91 92 #ifdef CONFIG_SPL_BUILD 93 #ifdef CONFIG_SPL_OS_BOOT 94 int spl_start_uboot(void) 95 { 96 debug("SPL: booting kernel\n"); 97 /* break into full u-boot on 'c' */ 98 return serial_tstc() && serial_getc() == 'c'; 99 } 100 #endif 101 102 int spl_dram_init(void) 103 { 104 struct udevice *dev; 105 int rv; 106 rv = uclass_get_device(UCLASS_RAM, 0, &dev); 107 if (rv) 108 debug("DRAM init failed: %d\n", rv); 109 return rv; 110 } 111 void spl_board_init(void) 112 { 113 spl_dram_init(); 114 preloader_console_init(); 115 arch_cpu_init(); /* to configure mpu for sdram rw permissions */ 116 } 117 u32 spl_boot_device(void) 118 { 119 return BOOT_DEVICE_XIP; 120 } 121 122 #endif 123 u32 get_board_rev(void) 124 { 125 return 0; 126 } 127 128 int board_late_init(void) 129 { 130 struct gpio_desc gpio = {}; 131 int node; 132 133 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,led1"); 134 if (node < 0) 135 return -1; 136 137 gpio_request_by_name_nodev(offset_to_ofnode(node), "led-gpio", 0, &gpio, 138 GPIOD_IS_OUT); 139 140 if (dm_gpio_is_valid(&gpio)) { 141 dm_gpio_set_value(&gpio, 0); 142 mdelay(10); 143 dm_gpio_set_value(&gpio, 1); 144 } 145 146 /* read button 1*/ 147 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,button1"); 148 if (node < 0) 149 return -1; 150 151 gpio_request_by_name_nodev(offset_to_ofnode(node), "button-gpio", 0, 152 &gpio, GPIOD_IS_IN); 153 154 if (dm_gpio_is_valid(&gpio)) { 155 if (dm_gpio_get_value(&gpio)) 156 puts("usr button is at HIGH LEVEL\n"); 157 else 158 puts("usr button is at LOW LEVEL\n"); 159 } 160 161 return 0; 162 } 163 164 int board_init(void) 165 { 166 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; 167 return 0; 168 } 169