1 /* 2 * (C) Copyright 2016 3 * Vikas Manocha, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <asm/armv7m.h> 11 #include <asm/arch/stm32.h> 12 #include <asm/arch/gpio.h> 13 #include <asm/arch/fmc.h> 14 #include <dm/platdata.h> 15 #include <dm/platform_data/serial_stm32x7.h> 16 #include <asm/arch/stm32_periph.h> 17 #include <asm/arch/stm32_defs.h> 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 const struct stm32_gpio_ctl gpio_ctl_gpout = { 22 .mode = STM32_GPIO_MODE_OUT, 23 .otype = STM32_GPIO_OTYPE_PP, 24 .speed = STM32_GPIO_SPEED_50M, 25 .pupd = STM32_GPIO_PUPD_NO, 26 .af = STM32_GPIO_AF0 27 }; 28 29 const struct stm32_gpio_ctl gpio_ctl_usart = { 30 .mode = STM32_GPIO_MODE_AF, 31 .otype = STM32_GPIO_OTYPE_PP, 32 .speed = STM32_GPIO_SPEED_50M, 33 .pupd = STM32_GPIO_PUPD_UP, 34 .af = STM32_GPIO_AF7 35 }; 36 37 const struct stm32_gpio_ctl gpio_ctl_fmc = { 38 .mode = STM32_GPIO_MODE_AF, 39 .otype = STM32_GPIO_OTYPE_PP, 40 .speed = STM32_GPIO_SPEED_100M, 41 .pupd = STM32_GPIO_PUPD_NO, 42 .af = STM32_GPIO_AF12 43 }; 44 45 static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { 46 /* Chip is LQFP144, see DM00077036.pdf for details */ 47 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ 48 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ 49 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ 50 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ 51 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ 52 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ 53 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ 54 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ 55 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ 56 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ 57 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ 58 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ 59 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ 60 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ 61 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ 62 {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ 63 64 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ 65 {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ 66 67 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ 68 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ 69 70 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ 71 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ 72 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ 73 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ 74 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ 75 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ 76 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ 77 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ 78 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ 79 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ 80 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ 81 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ 82 83 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */ 84 {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ 85 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ 86 {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */ 87 {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */ 88 89 {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ 90 }; 91 92 static int fmc_setup_gpio(void) 93 { 94 int rv = 0; 95 int i; 96 97 clock_setup(GPIO_B_CLOCK_CFG); 98 clock_setup(GPIO_C_CLOCK_CFG); 99 clock_setup(GPIO_D_CLOCK_CFG); 100 clock_setup(GPIO_E_CLOCK_CFG); 101 clock_setup(GPIO_F_CLOCK_CFG); 102 clock_setup(GPIO_G_CLOCK_CFG); 103 clock_setup(GPIO_H_CLOCK_CFG); 104 105 for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { 106 rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], 107 &gpio_ctl_fmc); 108 if (rv) 109 goto out; 110 } 111 112 out: 113 return rv; 114 } 115 116 static inline u32 _ns2clk(u32 ns, u32 freq) 117 { 118 u32 tmp = freq/1000000; 119 return (tmp * ns) / 1000; 120 } 121 122 #define NS2CLK(ns) (_ns2clk(ns, freq)) 123 124 /* 125 * Following are timings for IS42S16400J, from corresponding datasheet 126 */ 127 #define SDRAM_CAS 3 /* 3 cycles */ 128 #define SDRAM_NB 1 /* Number of banks */ 129 #define SDRAM_MWID 1 /* 16 bit memory */ 130 131 #define SDRAM_NR 0x1 /* 12-bit row */ 132 #define SDRAM_NC 0x0 /* 8-bit col */ 133 #define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ 134 #define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ 135 136 #define SDRAM_TRRD NS2CLK(12) 137 #define SDRAM_TRCD NS2CLK(18) 138 #define SDRAM_TRP NS2CLK(18) 139 #define SDRAM_TRAS NS2CLK(42) 140 #define SDRAM_TRC NS2CLK(60) 141 #define SDRAM_TRFC NS2CLK(60) 142 #define SDRAM_TCDL (1 - 1) 143 #define SDRAM_TRDL NS2CLK(12) 144 #define SDRAM_TBDL (1 - 1) 145 #define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) 146 #define SDRAM_TCCD (1 - 1) 147 148 #define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ 149 #define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ 150 151 152 /* Last data in to row precharge, need also comply ineq on page 1648 */ 153 #define SDRAM_TWR max(\ 154 (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ 155 (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ 156 ) 157 158 159 #define SDRAM_MODE_BL_SHIFT 0 160 #define SDRAM_MODE_CAS_SHIFT 4 161 #define SDRAM_MODE_BL 0 162 #define SDRAM_MODE_CAS SDRAM_CAS 163 164 int dram_init(void) 165 { 166 u32 freq; 167 int rv; 168 169 rv = fmc_setup_gpio(); 170 if (rv) 171 return rv; 172 173 clock_setup(FMC_CLOCK_CFG); 174 175 /* 176 * Get frequency for NS2CLK calculation. 177 */ 178 freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; 179 180 writel( 181 CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT 182 | SDRAM_CAS << FMC_SDCR_CAS_SHIFT 183 | SDRAM_NB << FMC_SDCR_NB_SHIFT 184 | SDRAM_MWID << FMC_SDCR_MWID_SHIFT 185 | SDRAM_NR << FMC_SDCR_NR_SHIFT 186 | SDRAM_NC << FMC_SDCR_NC_SHIFT 187 | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT 188 | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, 189 &STM32_SDRAM_FMC->sdcr1); 190 191 writel( 192 SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT 193 | SDRAM_TRP << FMC_SDTR_TRP_SHIFT 194 | SDRAM_TWR << FMC_SDTR_TWR_SHIFT 195 | SDRAM_TRC << FMC_SDTR_TRC_SHIFT 196 | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT 197 | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT 198 | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, 199 &STM32_SDRAM_FMC->sdtr1); 200 201 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, 202 &STM32_SDRAM_FMC->sdcmr); 203 204 udelay(200); /* 200 us delay, page 10, "Power-Up" */ 205 FMC_BUSY_WAIT(); 206 207 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, 208 &STM32_SDRAM_FMC->sdcmr); 209 210 udelay(100); 211 FMC_BUSY_WAIT(); 212 213 writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH 214 | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); 215 216 udelay(100); 217 FMC_BUSY_WAIT(); 218 219 writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT 220 | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) 221 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, 222 &STM32_SDRAM_FMC->sdcmr); 223 224 udelay(100); 225 226 FMC_BUSY_WAIT(); 227 228 writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, 229 &STM32_SDRAM_FMC->sdcmr); 230 231 FMC_BUSY_WAIT(); 232 233 /* Refresh timer */ 234 writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); 235 236 /* 237 * Fill in global info with description of SRAM configuration 238 */ 239 gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; 240 gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; 241 242 gd->ram_size = CONFIG_SYS_RAM_SIZE; 243 244 return rv; 245 } 246 247 static const struct stm32_gpio_dsc usart_gpio[] = { 248 {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ 249 {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */ 250 }; 251 252 int uart_setup_gpio(void) 253 { 254 int i; 255 int rv = 0; 256 257 clock_setup(GPIO_A_CLOCK_CFG); 258 clock_setup(GPIO_B_CLOCK_CFG); 259 for (i = 0; i < ARRAY_SIZE(usart_gpio); i++) { 260 rv = stm32_gpio_config(&usart_gpio[i], &gpio_ctl_usart); 261 if (rv) 262 goto out; 263 } 264 265 out: 266 return rv; 267 } 268 269 static const struct stm32x7_serial_platdata serial_platdata = { 270 .base = (struct stm32_usart *)USART1_BASE, 271 .clock = CONFIG_SYS_CLK_FREQ, 272 }; 273 274 U_BOOT_DEVICE(stm32x7_serials) = { 275 .name = "serial_stm32x7", 276 .platdata = &serial_platdata, 277 }; 278 279 u32 get_board_rev(void) 280 { 281 return 0; 282 } 283 284 int board_early_init_f(void) 285 { 286 int res; 287 288 res = uart_setup_gpio(); 289 clock_setup(USART1_CLOCK_CFG); 290 if (res) 291 return res; 292 293 return 0; 294 } 295 296 int board_init(void) 297 { 298 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 299 300 return 0; 301 } 302