1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2015 Stefan Roese <sr@denx.de> 4 */ 5 6 #include <common.h> 7 #include <i2c.h> 8 #include <miiphy.h> 9 #include <netdev.h> 10 #include <asm/io.h> 11 #include <asm/arch/cpu.h> 12 #include <asm/arch/soc.h> 13 14 #include "../drivers/ddr/marvell/a38x/ddr3_init.h" 15 #include <../serdes/a38x/high_speed_env_spec.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 #define ETH_PHY_CTRL_REG 0 20 #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 21 #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) 22 23 /* 24 * Those values and defines are taken from the Marvell U-Boot version 25 * "u-boot-2013.01-15t1-clearfog" 26 */ 27 #define BOARD_GPP_OUT_ENA_LOW 0xffffffff 28 #define BOARD_GPP_OUT_ENA_MID 0xffffffff 29 30 #define BOARD_GPP_OUT_VAL_LOW 0x0 31 #define BOARD_GPP_OUT_VAL_MID 0x0 32 #define BOARD_GPP_POL_LOW 0x0 33 #define BOARD_GPP_POL_MID 0x0 34 35 /* IO expander on Marvell GP board includes e.g. fan enabling */ 36 struct marvell_io_exp { 37 u8 chip; 38 u8 addr; 39 u8 val; 40 }; 41 42 static struct marvell_io_exp io_exp[] = { 43 { 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */ 44 { 0x20, 6, 0xf9 }, 45 { 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */ 46 { 0x20, 6, 0xb9 }, 47 { 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */ 48 { 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */ 49 }; 50 51 static struct serdes_map board_serdes_map[] = { 52 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 53 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 54 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 55 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 56 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, 57 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, 58 }; 59 60 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) 61 { 62 *serdes_map_array = board_serdes_map; 63 *count = ARRAY_SIZE(board_serdes_map); 64 return 0; 65 } 66 67 /* 68 * Define the DDR layout / topology here in the board file. This will 69 * be used by the DDR3 init code in the SPL U-Boot version to configure 70 * the DDR3 controller. 71 */ 72 static struct mv_ddr_topology_map board_topology_map = { 73 DEBUG_LEVEL_ERROR, 74 0x1, /* active interfaces */ 75 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ 76 { { { {0x1, 0, 0, 0}, 77 {0x1, 0, 0, 0}, 78 {0x1, 0, 0, 0}, 79 {0x1, 0, 0, 0}, 80 {0x1, 0, 0, 0} }, 81 SPEED_BIN_DDR_1600K, /* speed_bin */ 82 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ 83 MV_DDR_DIE_CAP_4GBIT, /* mem_size */ 84 DDR_FREQ_800, /* frequency */ 85 0, 0, /* cas_wl cas_l */ 86 MV_DDR_TEMP_LOW} }, /* temperature */ 87 BUS_MASK_32BIT, /* Busses mask */ 88 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ 89 { {0} }, /* raw spd data */ 90 {0} /* timing parameters */ 91 }; 92 93 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) 94 { 95 /* Return the board topology as defined in the board code */ 96 return &board_topology_map; 97 } 98 99 int board_early_init_f(void) 100 { 101 /* Configure MPP */ 102 writel(0x11111111, MVEBU_MPP_BASE + 0x00); 103 writel(0x11111111, MVEBU_MPP_BASE + 0x04); 104 writel(0x10400011, MVEBU_MPP_BASE + 0x08); 105 writel(0x22043333, MVEBU_MPP_BASE + 0x0c); 106 writel(0x44400002, MVEBU_MPP_BASE + 0x10); 107 writel(0x41144004, MVEBU_MPP_BASE + 0x14); 108 writel(0x40333333, MVEBU_MPP_BASE + 0x18); 109 writel(0x00004444, MVEBU_MPP_BASE + 0x1c); 110 111 /* Set GPP Out value */ 112 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); 113 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); 114 115 /* Set GPP Polarity */ 116 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); 117 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); 118 119 /* Set GPP Out Enable */ 120 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); 121 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); 122 123 return 0; 124 } 125 126 int board_init(void) 127 { 128 int i; 129 130 /* Address of boot parameters */ 131 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; 132 133 /* Toggle GPIO41 to reset onboard switch and phy */ 134 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); 135 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); 136 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */ 137 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); 138 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19)); 139 mdelay(1); 140 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); 141 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); 142 mdelay(10); 143 144 /* Init I2C IO expanders */ 145 for (i = 0; i < ARRAY_SIZE(io_exp); i++) 146 i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); 147 148 return 0; 149 } 150 151 int checkboard(void) 152 { 153 puts("Board: SolidRun ClearFog\n"); 154 155 return 0; 156 } 157 158 int board_eth_init(bd_t *bis) 159 { 160 cpu_eth_init(bis); /* Built in controller(s) come first */ 161 return pci_eth_init(bis); 162 } 163