1 /* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. All rights reserved. 3 * Sanghee Kim <sh0130.kim@samsung.com> 4 * Piotr Wilczek <p.wilczek@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <lcd.h> 11 #include <asm/io.h> 12 #include <asm/arch/gpio.h> 13 #include <asm/arch/mmc.h> 14 #include <asm/arch/power.h> 15 #include <asm/arch/clk.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/mipi_dsim.h> 18 #include <asm/arch/pinmux.h> 19 #include <asm/arch/power.h> 20 #include <power/pmic.h> 21 #include <power/max77686_pmic.h> 22 #include <power/battery.h> 23 #include <power/max77693_pmic.h> 24 #include <power/max77693_muic.h> 25 #include <power/max77693_fg.h> 26 #include <libtizen.h> 27 #include <errno.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 static struct exynos4x12_gpio_part1 *gpio1; 32 static struct exynos4x12_gpio_part2 *gpio2; 33 34 static unsigned int board_rev = -1; 35 36 static inline u32 get_model_rev(void); 37 38 static void check_hw_revision(void) 39 { 40 int modelrev = 0; 41 int i; 42 43 gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; 44 45 /* 46 * GPM1[1:0]: MODEL_REV[1:0] 47 * Don't set as pull-none for these N/C pin. 48 * TRM say that it may cause unexcepted state and leakage current. 49 * and pull-none is only for output function. 50 */ 51 for (i = 0; i < 2; i++) 52 s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); 53 54 /* GPM1[5:2]: HW_REV[3:0] */ 55 for (i = 2; i < 6; i++) { 56 s5p_gpio_cfg_pin(&gpio2->m1, i, GPIO_INPUT); 57 s5p_gpio_set_pull(&gpio2->m1, i, GPIO_PULL_NONE); 58 } 59 60 /* GPM1[1:0]: MODEL_REV[1:0] */ 61 for (i = 0; i < 2; i++) 62 modelrev |= (s5p_gpio_get_value(&gpio2->m1, i) << i); 63 64 /* board_rev[15:8] = model */ 65 board_rev = modelrev << 8; 66 } 67 68 #ifdef CONFIG_DISPLAY_BOARDINFO 69 int checkboard(void) 70 { 71 puts("Board:\tTRATS2\n"); 72 return 0; 73 } 74 #endif 75 76 static void show_hw_revision(void) 77 { 78 printf("HW Revision:\t0x%04x\n", board_rev); 79 } 80 81 u32 get_board_rev(void) 82 { 83 return board_rev; 84 } 85 86 static inline u32 get_model_rev(void) 87 { 88 return (board_rev >> 8) & 0xff; 89 } 90 91 static void board_external_gpio_init(void) 92 { 93 gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; 94 95 /* 96 * some pins which in alive block are connected with external pull-up 97 * but it's default setting is pull-down. 98 * if that pin set as input then that floated 99 */ 100 101 s5p_gpio_set_pull(&gpio2->x0, 2, GPIO_PULL_NONE); /* PS_ALS_INT */ 102 s5p_gpio_set_pull(&gpio2->x0, 4, GPIO_PULL_NONE); /* TSP_nINT */ 103 s5p_gpio_set_pull(&gpio2->x0, 7, GPIO_PULL_NONE); /* AP_PMIC_IRQ*/ 104 s5p_gpio_set_pull(&gpio2->x1, 5, GPIO_PULL_NONE); /* IF_PMIC_IRQ*/ 105 s5p_gpio_set_pull(&gpio2->x2, 0, GPIO_PULL_NONE); /* VOL_UP */ 106 s5p_gpio_set_pull(&gpio2->x2, 1, GPIO_PULL_NONE); /* VOL_DOWN */ 107 s5p_gpio_set_pull(&gpio2->x2, 3, GPIO_PULL_NONE); /* FUEL_ALERT */ 108 s5p_gpio_set_pull(&gpio2->x2, 4, GPIO_PULL_NONE); /* ADC_INT */ 109 s5p_gpio_set_pull(&gpio2->x2, 7, GPIO_PULL_NONE); /* nPOWER */ 110 s5p_gpio_set_pull(&gpio2->x3, 0, GPIO_PULL_NONE); /* WPC_INT */ 111 s5p_gpio_set_pull(&gpio2->x3, 5, GPIO_PULL_NONE); /* OK_KEY */ 112 s5p_gpio_set_pull(&gpio2->x3, 7, GPIO_PULL_NONE); /* HDMI_HPD */ 113 } 114 115 #ifdef CONFIG_SYS_I2C_INIT_BOARD 116 static void board_init_i2c(void) 117 { 118 gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; 119 gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; 120 121 /* I2C_7 */ 122 s5p_gpio_direction_output(&gpio1->d0, 2, 1); 123 s5p_gpio_direction_output(&gpio1->d0, 3, 1); 124 125 /* I2C_8 */ 126 s5p_gpio_direction_output(&gpio1->f1, 4, 1); 127 s5p_gpio_direction_output(&gpio1->f1, 5, 1); 128 129 /* I2C_9 */ 130 s5p_gpio_direction_output(&gpio2->m2, 1, 1); 131 s5p_gpio_direction_output(&gpio2->m2, 0, 1); 132 } 133 #endif 134 135 int board_early_init_f(void) 136 { 137 check_hw_revision(); 138 board_external_gpio_init(); 139 140 gd->flags |= GD_FLG_DISABLE_CONSOLE; 141 142 return 0; 143 } 144 145 static int pmic_init_max77686(void); 146 147 int board_init(void) 148 { 149 struct exynos4_power *pwr = 150 (struct exynos4_power *)EXYNOS4X12_POWER_BASE; 151 152 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 153 154 /* workaround: clear INFORM4..5 */ 155 writel(0, (unsigned int)&pwr->inform4); 156 writel(0, (unsigned int)&pwr->inform5); 157 158 return 0; 159 } 160 161 int power_init_board(void) 162 { 163 int chrg; 164 struct power_battery *pb; 165 struct pmic *p_chrg, *p_muic, *p_fg, *p_bat; 166 167 #ifdef CONFIG_SYS_I2C_INIT_BOARD 168 board_init_i2c(); 169 #endif 170 pmic_init(I2C_0); /* I2C adapter 0 - bus name I2C_5 */ 171 pmic_init_max77686(); 172 pmic_init_max77693(I2C_2); /* I2C adapter 2 - bus name I2C_10 */ 173 power_muic_init(I2C_2); /* I2C adapter 2 - bus name I2C_10 */ 174 power_fg_init(I2C_1); /* I2C adapter 1 - bus name I2C_9 */ 175 power_bat_init(0); 176 177 p_chrg = pmic_get("MAX77693_PMIC"); 178 if (!p_chrg) { 179 puts("MAX77693_PMIC: Not found\n"); 180 return -ENODEV; 181 } 182 183 p_muic = pmic_get("MAX77693_MUIC"); 184 if (!p_muic) { 185 puts("MAX77693_MUIC: Not found\n"); 186 return -ENODEV; 187 } 188 189 p_fg = pmic_get("MAX77693_FG"); 190 if (!p_fg) { 191 puts("MAX17042_FG: Not found\n"); 192 return -ENODEV; 193 } 194 195 if (p_chrg->chrg->chrg_bat_present(p_chrg) == 0) 196 puts("No battery detected\n"); 197 198 p_bat = pmic_get("BAT_TRATS2"); 199 if (!p_bat) { 200 puts("BAT_TRATS2: Not found\n"); 201 return -ENODEV; 202 } 203 204 p_fg->parent = p_bat; 205 p_chrg->parent = p_bat; 206 p_muic->parent = p_bat; 207 208 p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); 209 210 pb = p_bat->pbat; 211 chrg = p_muic->chrg->chrg_type(p_muic); 212 debug("CHARGER TYPE: %d\n", chrg); 213 214 if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { 215 puts("No battery detected\n"); 216 return -1; 217 } 218 219 p_fg->fg->fg_battery_check(p_fg, p_bat); 220 221 if (pb->bat->state == CHARGE && chrg == CHARGER_USB) 222 puts("CHARGE Battery !\n"); 223 224 return 0; 225 } 226 227 int dram_init(void) 228 { 229 u32 size_mb; 230 231 size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + 232 get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + 233 get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + 234 get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20; 235 236 gd->ram_size = size_mb << 20; 237 238 return 0; 239 } 240 241 void dram_init_banksize(void) 242 { 243 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 244 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; 245 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 246 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; 247 gd->bd->bi_dram[2].start = PHYS_SDRAM_3; 248 gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; 249 gd->bd->bi_dram[3].start = PHYS_SDRAM_4; 250 gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; 251 } 252 253 int board_mmc_init(bd_t *bis) 254 { 255 int err0, err2 = 0; 256 257 gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE; 258 259 /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */ 260 s5p_gpio_direction_output(&gpio2->k0, 2, 1); 261 s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE); 262 263 /* 264 * eMMC GPIO: 265 * SDR 8-bit@48MHz at MMC0 266 * GPK0[0] SD_0_CLK(2) 267 * GPK0[1] SD_0_CMD(2) 268 * GPK0[2] SD_0_CDn -> Not used 269 * GPK0[3:6] SD_0_DATA[0:3](2) 270 * GPK1[3:6] SD_0_DATA[0:3](3) 271 * 272 * DDR 4-bit@26MHz at MMC4 273 * GPK0[0] SD_4_CLK(3) 274 * GPK0[1] SD_4_CMD(3) 275 * GPK0[2] SD_4_CDn -> Not used 276 * GPK0[3:6] SD_4_DATA[0:3](3) 277 * GPK1[3:6] SD_4_DATA[4:7](4) 278 */ 279 280 err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); 281 282 /* 283 * MMC device init 284 * mmc0 : eMMC (8-bit buswidth) 285 * mmc2 : SD card (4-bit buswidth) 286 */ 287 if (err0) 288 debug("SDMMC0 not configured\n"); 289 else 290 err0 = s5p_mmc_init(0, 8); 291 292 /* T-flash detect */ 293 s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); 294 s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); 295 296 /* 297 * Check the T-flash detect pin 298 * GPX3[4] T-flash detect pin 299 */ 300 if (!s5p_gpio_get_value(&gpio2->x3, 4)) { 301 err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE); 302 if (err2) 303 debug("SDMMC2 not configured\n"); 304 else 305 err2 = s5p_mmc_init(2, 4); 306 } 307 308 return err0 & err2; 309 } 310 311 static int pmic_init_max77686(void) 312 { 313 struct pmic *p = pmic_get("MAX77686_PMIC"); 314 315 if (pmic_probe(p)) 316 return -1; 317 318 /* BUCK/LDO Output Voltage */ 319 max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 VTF_2.8V */ 320 max77686_set_ldo_voltage(p, 23, 3300000); /* LDO23 TSP_AVDD_3.3V*/ 321 max77686_set_ldo_voltage(p, 24, 1800000); /* LDO24 TSP_VDD_1.8V */ 322 323 /* BUCK/LDO Output Mode */ 324 max77686_set_buck_mode(p, 1, OPMODE_STANDBY); /* BUCK1 VMIF_1.1V_AP */ 325 max77686_set_buck_mode(p, 2, OPMODE_ON); /* BUCK2 VARM_1.0V_AP */ 326 max77686_set_buck_mode(p, 3, OPMODE_ON); /* BUCK3 VINT_1.0V_AP */ 327 max77686_set_buck_mode(p, 4, OPMODE_ON); /* BUCK4 VG3D_1.0V_AP */ 328 max77686_set_buck_mode(p, 5, OPMODE_ON); /* BUCK5 VMEM_1.2V_AP */ 329 max77686_set_buck_mode(p, 6, OPMODE_ON); /* BUCK6 VCC_SUB_1.35V*/ 330 max77686_set_buck_mode(p, 7, OPMODE_ON); /* BUCK7 VCC_SUB_2.0V */ 331 max77686_set_buck_mode(p, 8, OPMODE_OFF); /* VMEM_VDDF_2.85V */ 332 max77686_set_buck_mode(p, 9, OPMODE_OFF); /* CAM_ISP_CORE_1.2V*/ 333 334 max77686_set_ldo_mode(p, 1, OPMODE_LPM); /* LDO1 VALIVE_1.0V_AP*/ 335 max77686_set_ldo_mode(p, 2, OPMODE_STANDBY); /* LDO2 VM1M2_1.2V_AP */ 336 max77686_set_ldo_mode(p, 3, OPMODE_LPM); /* LDO3 VCC_1.8V_AP */ 337 max77686_set_ldo_mode(p, 4, OPMODE_LPM); /* LDO4 VCC_2.8V_AP */ 338 max77686_set_ldo_mode(p, 5, OPMODE_OFF); /* LDO5_VCC_1.8V_IO */ 339 max77686_set_ldo_mode(p, 6, OPMODE_STANDBY); /* LDO6 VMPLL_1.0V_AP */ 340 max77686_set_ldo_mode(p, 7, OPMODE_STANDBY); /* LDO7 VPLL_1.0V_AP */ 341 max77686_set_ldo_mode(p, 8, OPMODE_LPM); /* LDO8 VMIPI_1.0V_AP */ 342 max77686_set_ldo_mode(p, 9, OPMODE_OFF); /* CAM_ISP_MIPI_1.2*/ 343 max77686_set_ldo_mode(p, 10, OPMODE_LPM); /* LDO10 VMIPI_1.8V_AP*/ 344 max77686_set_ldo_mode(p, 11, OPMODE_STANDBY); /* LDO11 VABB1_1.8V_AP*/ 345 max77686_set_ldo_mode(p, 12, OPMODE_LPM); /* LDO12 VUOTG_3.0V_AP*/ 346 max77686_set_ldo_mode(p, 13, OPMODE_OFF); /* LDO13 VC2C_1.8V_AP */ 347 max77686_set_ldo_mode(p, 14, OPMODE_STANDBY); /* VABB02_1.8V_AP */ 348 max77686_set_ldo_mode(p, 15, OPMODE_STANDBY); /* LDO15 VHSIC_1.0V_AP*/ 349 max77686_set_ldo_mode(p, 16, OPMODE_STANDBY); /* LDO16 VHSIC_1.8V_AP*/ 350 max77686_set_ldo_mode(p, 17, OPMODE_OFF); /* CAM_SENSOR_CORE_1.2*/ 351 max77686_set_ldo_mode(p, 18, OPMODE_OFF); /* CAM_ISP_SEN_IO_1.8V*/ 352 max77686_set_ldo_mode(p, 19, OPMODE_OFF); /* LDO19 VT_CAM_1.8V */ 353 max77686_set_ldo_mode(p, 20, OPMODE_ON); /* LDO20 VDDQ_PRE_1.8V*/ 354 max77686_set_ldo_mode(p, 21, OPMODE_OFF); /* LDO21 VTF_2.8V */ 355 max77686_set_ldo_mode(p, 22, OPMODE_OFF); /* LDO22 VMEM_VDD_2.8V*/ 356 max77686_set_ldo_mode(p, 23, OPMODE_OFF); /* LDO23 TSP_AVDD_3.3V*/ 357 max77686_set_ldo_mode(p, 24, OPMODE_OFF); /* LDO24 TSP_VDD_1.8V */ 358 max77686_set_ldo_mode(p, 25, OPMODE_OFF); /* LDO25 VCC_3.3V_LCD */ 359 max77686_set_ldo_mode(p, 26, OPMODE_OFF); /*LDO26 VCC_3.0V_MOTOR*/ 360 361 return 0; 362 } 363 364 /* 365 * LCD 366 */ 367 368 #ifdef CONFIG_LCD 369 static struct mipi_dsim_config dsim_config = { 370 .e_interface = DSIM_VIDEO, 371 .e_virtual_ch = DSIM_VIRTUAL_CH_0, 372 .e_pixel_format = DSIM_24BPP_888, 373 .e_burst_mode = DSIM_BURST_SYNC_EVENT, 374 .e_no_data_lane = DSIM_DATA_LANE_4, 375 .e_byte_clk = DSIM_PLL_OUT_DIV8, 376 .hfp = 1, 377 378 .p = 3, 379 .m = 120, 380 .s = 1, 381 382 /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */ 383 .pll_stable_time = 500, 384 385 /* escape clk : 10MHz */ 386 .esc_clk = 20 * 1000000, 387 388 /* stop state holding counter after bta change count 0 ~ 0xfff */ 389 .stop_holding_cnt = 0x7ff, 390 /* bta timeout 0 ~ 0xff */ 391 .bta_timeout = 0xff, 392 /* lp rx timeout 0 ~ 0xffff */ 393 .rx_timeout = 0xffff, 394 }; 395 396 static struct exynos_platform_mipi_dsim dsim_platform_data = { 397 .lcd_panel_info = NULL, 398 .dsim_config = &dsim_config, 399 }; 400 401 static struct mipi_dsim_lcd_device mipi_lcd_device = { 402 .name = "s6e8ax0", 403 .id = -1, 404 .bus_id = 0, 405 .platform_data = (void *)&dsim_platform_data, 406 }; 407 408 static int mipi_power(void) 409 { 410 struct pmic *p = pmic_get("MAX77686_PMIC"); 411 412 /* LDO8 VMIPI_1.0V_AP */ 413 max77686_set_ldo_mode(p, 8, OPMODE_ON); 414 /* LDO10 VMIPI_1.8V_AP */ 415 max77686_set_ldo_mode(p, 10, OPMODE_ON); 416 417 return 0; 418 } 419 420 void exynos_lcd_power_on(void) 421 { 422 struct pmic *p = pmic_get("MAX77686_PMIC"); 423 424 gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; 425 426 /* LCD_2.2V_EN: GPC0[1] */ 427 s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP); 428 s5p_gpio_direction_output(&gpio1->c0, 1, 1); 429 430 /* LDO25 VCC_3.1V_LCD */ 431 pmic_probe(p); 432 max77686_set_ldo_voltage(p, 25, 3100000); 433 max77686_set_ldo_mode(p, 25, OPMODE_LPM); 434 } 435 436 void exynos_reset_lcd(void) 437 { 438 gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE; 439 440 /* reset lcd */ 441 s5p_gpio_direction_output(&gpio1->f2, 1, 0); 442 udelay(10); 443 s5p_gpio_set_value(&gpio1->f2, 1, 1); 444 } 445 446 vidinfo_t panel_info = { 447 .vl_freq = 60, 448 .vl_col = 720, 449 .vl_row = 1280, 450 .vl_width = 720, 451 .vl_height = 1280, 452 .vl_clkp = CONFIG_SYS_HIGH, 453 .vl_hsp = CONFIG_SYS_LOW, 454 .vl_vsp = CONFIG_SYS_LOW, 455 .vl_dp = CONFIG_SYS_LOW, 456 .vl_bpix = 5, /* Bits per pixel, 2^5 = 32 */ 457 458 /* s6e8ax0 Panel infomation */ 459 .vl_hspw = 5, 460 .vl_hbpd = 10, 461 .vl_hfpd = 10, 462 463 .vl_vspw = 2, 464 .vl_vbpd = 1, 465 .vl_vfpd = 13, 466 .vl_cmd_allow_len = 0xf, 467 .mipi_enabled = 1, 468 469 .dual_lcd_enabled = 0, 470 471 .init_delay = 0, 472 .power_on_delay = 25, 473 .reset_delay = 0, 474 .interface_mode = FIMD_RGB_INTERFACE, 475 }; 476 477 void init_panel_info(vidinfo_t *vid) 478 { 479 vid->logo_on = 1; 480 vid->resolution = HD_RESOLUTION; 481 vid->rgb_mode = MODE_RGB_P; 482 483 vid->power_on_delay = 30; 484 485 mipi_lcd_device.reverse_panel = 1; 486 487 #ifdef CONFIG_TIZEN 488 get_tizen_logo_info(vid); 489 #endif 490 491 strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name); 492 dsim_platform_data.mipi_power = mipi_power; 493 dsim_platform_data.phy_enable = set_mipi_phy_ctrl; 494 dsim_platform_data.lcd_panel_info = (void *)vid; 495 exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device); 496 497 s6e8ax0_init(); 498 499 exynos_set_dsim_platform_data(&dsim_platform_data); 500 } 501 #endif /* LCD */ 502 503 #ifdef CONFIG_MISC_INIT_R 504 int misc_init_r(void) 505 { 506 setenv("model", "GT-I8800"); 507 setenv("board", "TRATS2"); 508 509 show_hw_revision(); 510 511 return 0; 512 } 513 #endif 514