1 /* 2 * board/renesas/silk/silk.c 3 * 4 * Copyright (C) 2015 Renesas Electronics Corporation 5 * Copyright (C) 2015 Cogent Embedded, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <dm.h> 13 #include <dm/platform_data/serial_sh.h> 14 #include <environment.h> 15 #include <asm/processor.h> 16 #include <asm/mach-types.h> 17 #include <asm/io.h> 18 #include <linux/errno.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/gpio.h> 21 #include <asm/arch/rmobile.h> 22 #include <asm/arch/rcar-mstp.h> 23 #include <asm/arch/mmc.h> 24 #include <asm/arch/sh_sdhi.h> 25 #include <netdev.h> 26 #include <miiphy.h> 27 #include <i2c.h> 28 #include <div64.h> 29 #include "qos.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define CLK2MHZ(clk) (clk / 1000 / 1000) 34 void s_init(void) 35 { 36 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 37 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 38 39 /* Watchdog init */ 40 writel(0xA5A5A500, &rwdt->rwtcsra); 41 writel(0xA5A5A500, &swdt->swtcsra); 42 43 /* QoS */ 44 qos_init(); 45 } 46 47 #define TMU0_MSTP125 (1 << 25) 48 #define SCIF2_MSTP719 (1 << 19) 49 #define ETHER_MSTP813 (1 << 13) 50 #define IIC1_MSTP323 (1 << 23) 51 #define MMC0_MSTP315 (1 << 15) 52 #define SDHI1_MSTP312 (1 << 12) 53 54 #define SD1CKCR 0xE6150078 55 #define SD1_97500KHZ 0x7 56 57 int board_early_init_f(void) 58 { 59 /* TMU */ 60 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 61 62 /* SCIF2 */ 63 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); 64 65 /* ETHER */ 66 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 67 68 /* IIC1 / sh-i2c ch1 */ 69 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); 70 71 #ifdef CONFIG_SH_MMCIF 72 /* MMC */ 73 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); 74 #endif 75 76 #ifdef CONFIG_SH_SDHI 77 /* SDHI1 */ 78 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI1_MSTP312); 79 80 /* 81 * Set SD1 to the 97.5MHz 82 */ 83 writel(SD1_97500KHZ, SD1CKCR); 84 #endif 85 return 0; 86 } 87 88 /* LSI pin pull-up control */ 89 #define PUPR3 0xe606010C 90 #define PUPR3_ETH 0x006FF800 91 #define PUPR1 0xe6060104 92 #define PUPR1_DREQ0_N (1 << 20) 93 int board_init(void) 94 { 95 /* adress of boot parameters */ 96 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 97 98 /* Init PFC controller */ 99 r8a7794_pinmux_init(); 100 101 /* Ether Enable */ 102 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 103 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 104 gpio_request(GPIO_FN_ETH_RXD0, NULL); 105 gpio_request(GPIO_FN_ETH_RXD1, NULL); 106 gpio_request(GPIO_FN_ETH_LINK, NULL); 107 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 108 gpio_request(GPIO_FN_ETH_MDIO, NULL); 109 gpio_request(GPIO_FN_ETH_TXD1, NULL); 110 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 111 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 112 gpio_request(GPIO_FN_ETH_TXD0, NULL); 113 gpio_request(GPIO_FN_ETH_MDC, NULL); 114 gpio_request(GPIO_FN_IRQ8, NULL); 115 116 /* PHY reset */ 117 mstp_clrbits_le32(PUPR3, PUPR3, PUPR3_ETH); 118 gpio_request(GPIO_GP_1_24, NULL); 119 mstp_clrbits_le32(PUPR1, PUPR1, PUPR1_DREQ0_N); 120 121 gpio_direction_output(GPIO_GP_1_24, 0); 122 mdelay(20); 123 gpio_set_value(GPIO_GP_1_24, 1); 124 udelay(1); 125 126 return 0; 127 } 128 129 #define CXR24 0xEE7003C0 /* MAC address high register */ 130 #define CXR25 0xEE7003C8 /* MAC address low register */ 131 int board_eth_init(bd_t *bis) 132 { 133 #ifdef CONFIG_SH_ETHER 134 int ret = -ENODEV; 135 u32 val; 136 unsigned char enetaddr[6]; 137 138 ret = sh_eth_initialize(bis); 139 if (!eth_env_get_enetaddr("ethaddr", enetaddr)) 140 return ret; 141 142 /* Set Mac address */ 143 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 144 enetaddr[2] << 8 | enetaddr[3]; 145 writel(val, CXR24); 146 147 val = enetaddr[4] << 8 | enetaddr[5]; 148 writel(val, CXR25); 149 150 return ret; 151 #else 152 return 0; 153 #endif 154 } 155 156 int board_mmc_init(bd_t *bis) 157 { 158 int ret = -ENODEV; 159 160 #ifdef CONFIG_SH_MMCIF 161 /* MMC0 */ 162 gpio_request(GPIO_GP_4_31, NULL); 163 gpio_direction_output(GPIO_GP_4_31, 1); 164 165 ret = mmcif_mmc_init(); 166 #endif 167 168 #ifdef CONFIG_SH_SDHI 169 gpio_request(GPIO_FN_SD1_DATA0, NULL); 170 gpio_request(GPIO_FN_SD1_DATA1, NULL); 171 gpio_request(GPIO_FN_SD1_DATA2, NULL); 172 gpio_request(GPIO_FN_SD1_DATA3, NULL); 173 gpio_request(GPIO_FN_SD1_CLK, NULL); 174 gpio_request(GPIO_FN_SD1_CMD, NULL); 175 gpio_request(GPIO_FN_SD1_CD, NULL); 176 177 /* SDHI 1 */ 178 gpio_request(GPIO_GP_4_26, NULL); 179 gpio_request(GPIO_GP_4_29, NULL); 180 gpio_direction_output(GPIO_GP_4_26, 1); 181 gpio_direction_output(GPIO_GP_4_29, 1); 182 183 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); 184 #endif 185 return ret; 186 } 187 188 int dram_init(void) 189 { 190 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 191 192 return 0; 193 } 194 195 const struct rmobile_sysinfo sysinfo = { 196 CONFIG_ARCH_RMOBILE_BOARD_STRING 197 }; 198 199 void reset_cpu(ulong addr) 200 { 201 u8 val; 202 203 i2c_set_bus_num(1); /* PowerIC connected to ch1 */ 204 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 205 val |= 0x02; 206 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 207 } 208 209 static const struct sh_serial_platdata serial_platdata = { 210 .base = SCIF2_BASE, 211 .type = PORT_SCIF, 212 .clk = 14745600, 213 .clk_mode = EXT_CLK, 214 }; 215 216 U_BOOT_DEVICE(silk_serials) = { 217 .name = "serial_sh", 218 .platdata = &serial_platdata, 219 }; 220