1 /* 2 * Copyright (C) 2012 Renesas Solutions Corp. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <environment.h> 9 #include <malloc.h> 10 #include <asm/processor.h> 11 #include <asm/io.h> 12 #include <asm/mmc.h> 13 #include <spi.h> 14 #include <spi_flash.h> 15 16 int checkboard(void) 17 { 18 puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n"); 19 20 return 0; 21 } 22 23 static void init_gpio(void) 24 { 25 struct gpio_regs *gpio = GPIO_BASE; 26 struct sermux_regs *sermux = SERMUX_BASE; 27 28 /* GPIO */ 29 writew(0x0000, &gpio->pacr); /* GETHER */ 30 writew(0x0001, &gpio->pbcr); /* INTC */ 31 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ 32 writew(0xeaff, &gpio->pecr); /* GPIO */ 33 writew(0x0000, &gpio->pfcr); /* WDT */ 34 writew(0x0000, &gpio->phcr); /* SPI1 */ 35 writew(0x0000, &gpio->picr); /* SDHI */ 36 writew(0x0003, &gpio->pkcr); /* SerMux */ 37 writew(0x0000, &gpio->plcr); /* SerMux */ 38 writew(0x0000, &gpio->pmcr); /* RIIC */ 39 writew(0x0000, &gpio->pncr); /* USB, SGPIO */ 40 writew(0x0000, &gpio->pocr); /* SGPIO */ 41 writew(0xd555, &gpio->pqcr); /* GPIO */ 42 writew(0x0000, &gpio->prcr); /* RIIC */ 43 writew(0x0000, &gpio->pscr); /* RIIC */ 44 writeb(0x00, &gpio->pudr); 45 writew(0x5555, &gpio->pucr); /* Debug LED */ 46 writew(0x0000, &gpio->pvcr); /* RSPI */ 47 writew(0x0000, &gpio->pwcr); /* EVC */ 48 writew(0x0000, &gpio->pxcr); /* LBSC */ 49 writew(0x0000, &gpio->pycr); /* LBSC */ 50 writew(0x0000, &gpio->pzcr); /* eMMC */ 51 writew(0xfe00, &gpio->psel0); 52 writew(0xff00, &gpio->psel3); 53 writew(0x771f, &gpio->psel4); 54 writew(0x00ff, &gpio->psel6); 55 writew(0xfc00, &gpio->psel7); 56 57 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */ 58 } 59 60 static void init_usb_phy(void) 61 { 62 struct usb_common_regs *common0 = USB0_COMMON_BASE; 63 struct usb_common_regs *common1 = USB1_COMMON_BASE; 64 struct usb0_phy_regs *phy = USB0_PHY_BASE; 65 struct usb1_port_regs *port = USB1_PORT_BASE; 66 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE; 67 68 writew(0x0100, &phy->reset); /* set reset */ 69 /* port0 = USB0, port1 = USB1 */ 70 writew(0x0002, &phy->portsel); 71 writel(0x0001, &port->port1sel); /* port1 = Host */ 72 writew(0x0111, &phy->reset); /* clear reset */ 73 74 writew(0x4000, &common0->suspmode); 75 writew(0x4000, &common1->suspmode); 76 77 #if defined(__LITTLE_ENDIAN) 78 writel(0x00000000, &align->ehcidatac); 79 writel(0x00000000, &align->ohcidatac); 80 #endif 81 } 82 83 static void init_gether_mdio(void) 84 { 85 struct gpio_regs *gpio = GPIO_BASE; 86 87 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr); 88 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ 89 } 90 91 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string) 92 { 93 struct ether_mac_regs *ether; 94 unsigned char mac[6]; 95 unsigned long val; 96 97 eth_parse_enetaddr(mac_string, mac); 98 99 if (!channel) 100 ether = GETHER0_MAC_BASE; 101 else 102 ether = GETHER1_MAC_BASE; 103 104 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3]; 105 writel(val, ðer->mahr); 106 val = (mac[4] << 8) | mac[5]; 107 writel(val, ðer->malr); 108 } 109 110 /***************************************************************** 111 * This PMB must be set on this timing. The lowlevel_init is run on 112 * Area 0(phys 0x00000000), so we have to map it. 113 * 114 * The new PMB table is following: 115 * ent virt phys v sz c wt 116 * 0 0xa0000000 0x40000000 1 128M 0 1 117 * 1 0xa8000000 0x48000000 1 128M 0 1 118 * 2 0xb0000000 0x50000000 1 128M 0 1 119 * 3 0xb8000000 0x58000000 1 128M 0 1 120 * 4 0x80000000 0x40000000 1 128M 1 1 121 * 5 0x88000000 0x48000000 1 128M 1 1 122 * 6 0x90000000 0x50000000 1 128M 1 1 123 * 7 0x98000000 0x58000000 1 128M 1 1 124 */ 125 static void set_pmb_on_board_init(void) 126 { 127 struct mmu_regs *mmu = MMU_BASE; 128 129 /* clear ITLB */ 130 writel(0x00000004, &mmu->mmucr); 131 132 /* delete PMB for SPIBOOT */ 133 writel(0, PMB_ADDR_BASE(0)); 134 writel(0, PMB_DATA_BASE(0)); 135 136 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ 137 /* ppn ub v s1 s0 c wt */ 138 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0)); 139 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0)); 140 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2)); 141 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2)); 142 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3)); 143 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3)); 144 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4)); 145 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4)); 146 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6)); 147 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6)); 148 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7)); 149 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7)); 150 } 151 152 int board_init(void) 153 { 154 init_gpio(); 155 set_pmb_on_board_init(); 156 157 init_usb_phy(); 158 init_gether_mdio(); 159 160 return 0; 161 } 162 163 int board_mmc_init(bd_t *bis) 164 { 165 struct gpio_regs *gpio = GPIO_BASE; 166 167 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr); 168 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ 169 udelay(1); 170 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ 171 udelay(200); 172 173 return mmcif_mmc_init(); 174 } 175 176 static int get_sh_eth_mac_raw(unsigned char *buf, int size) 177 { 178 struct spi_flash *spi; 179 int ret; 180 181 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 182 if (spi == NULL) { 183 printf("%s: spi_flash probe failed.\n", __func__); 184 return 1; 185 } 186 187 ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf); 188 if (ret) { 189 printf("%s: spi_flash read failed.\n", __func__); 190 spi_flash_free(spi); 191 return 1; 192 } 193 spi_flash_free(spi); 194 195 return 0; 196 } 197 198 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf) 199 { 200 memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)], 201 SH7752EVB_ETHERNET_MAC_SIZE); 202 mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */ 203 204 return 0; 205 } 206 207 static void init_ethernet_mac(void) 208 { 209 char mac_string[64]; 210 char env_string[64]; 211 int i; 212 unsigned char *buf; 213 214 buf = malloc(256); 215 if (!buf) { 216 printf("%s: malloc failed.\n", __func__); 217 return; 218 } 219 get_sh_eth_mac_raw(buf, 256); 220 221 /* Gigabit Ethernet */ 222 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { 223 get_sh_eth_mac(i, mac_string, buf); 224 if (i == 0) 225 env_set("ethaddr", mac_string); 226 else { 227 sprintf(env_string, "eth%daddr", i); 228 env_set(env_string, mac_string); 229 } 230 set_mac_to_sh_giga_eth_register(i, mac_string); 231 } 232 233 free(buf); 234 } 235 236 int board_late_init(void) 237 { 238 init_ethernet_mac(); 239 240 return 0; 241 } 242 243 int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 244 { 245 int i, ret; 246 char mac_string[256]; 247 struct spi_flash *spi; 248 unsigned char *buf; 249 250 if (argc != 3) { 251 buf = malloc(256); 252 if (!buf) { 253 printf("%s: malloc failed.\n", __func__); 254 return 1; 255 } 256 257 get_sh_eth_mac_raw(buf, 256); 258 259 /* print current MAC address */ 260 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) { 261 get_sh_eth_mac(i, mac_string, buf); 262 printf("GETHERC ch%d = %s\n", i, mac_string); 263 } 264 free(buf); 265 return 0; 266 } 267 268 /* new setting */ 269 memset(mac_string, 0xff, sizeof(mac_string)); 270 sprintf(mac_string, "%s\t%s", 271 argv[1], argv[2]); 272 273 /* write MAC data to SPI rom */ 274 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); 275 if (!spi) { 276 printf("%s: spi_flash probe failed.\n", __func__); 277 return 1; 278 } 279 280 ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, 281 SH7752EVB_SPI_SECTOR_SIZE); 282 if (ret) { 283 printf("%s: spi_flash erase failed.\n", __func__); 284 return 1; 285 } 286 287 ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI, 288 sizeof(mac_string), mac_string); 289 if (ret) { 290 printf("%s: spi_flash write failed.\n", __func__); 291 spi_flash_free(spi); 292 return 1; 293 } 294 spi_flash_free(spi); 295 296 puts("The writing of the MAC address to SPI ROM was completed.\n"); 297 298 return 0; 299 } 300 301 U_BOOT_CMD( 302 write_mac, 3, 1, do_write_mac, 303 "write MAC address for GETHERC", 304 "[GETHERC ch0] [GETHERC ch1]\n" 305 ); 306