1 /* 2 * board/renesas/lager/lager.c 3 * This file is lager board support. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #include <common.h> 12 #include <environment.h> 13 #include <malloc.h> 14 #include <netdev.h> 15 #include <dm.h> 16 #include <dm/platform_data/serial_sh.h> 17 #include <asm/processor.h> 18 #include <asm/mach-types.h> 19 #include <asm/io.h> 20 #include <linux/errno.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/gpio.h> 23 #include <asm/arch/rmobile.h> 24 #include <asm/arch/rcar-mstp.h> 25 #include <asm/arch/mmc.h> 26 #include <asm/arch/sh_sdhi.h> 27 #include <miiphy.h> 28 #include <i2c.h> 29 #include <mmc.h> 30 #include "qos.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #define CLK2MHZ(clk) (clk / 1000 / 1000) 35 void s_init(void) 36 { 37 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 38 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 39 40 /* Watchdog init */ 41 writel(0xA5A5A500, &rwdt->rwtcsra); 42 writel(0xA5A5A500, &swdt->swtcsra); 43 44 /* CPU frequency setting. Set to 1.4GHz */ 45 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { 46 u32 stat = 0; 47 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) 48 << PLL0_STC_BIT; 49 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 50 51 do { 52 stat = readl(PLLECR) & PLL0ST; 53 } while (stat == 0x0); 54 } 55 56 /* QoS(Quality-of-Service) Init */ 57 qos_init(); 58 } 59 60 #define TMU0_MSTP125 BIT(25) 61 62 #define SD1CKCR 0xE6150078 63 #define SD2CKCR 0xE615026C 64 #define SD_97500KHZ 0x7 65 66 int board_early_init_f(void) 67 { 68 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 69 70 /* 71 * SD0 clock is set to 97.5MHz by default. 72 * Set SD1 and SD2 to the 97.5MHz as well. 73 */ 74 writel(SD_97500KHZ, SD1CKCR); 75 writel(SD_97500KHZ, SD2CKCR); 76 77 return 0; 78 } 79 80 #define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */ 81 82 int board_init(void) 83 { 84 /* adress of boot parameters */ 85 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 86 87 /* Force ethernet PHY out of reset */ 88 gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 89 gpio_direction_output(ETHERNET_PHY_RESET, 0); 90 mdelay(10); 91 gpio_direction_output(ETHERNET_PHY_RESET, 1); 92 93 return 0; 94 } 95 96 int dram_init(void) 97 { 98 if (fdtdec_setup_memory_size() != 0) 99 return -EINVAL; 100 101 return 0; 102 } 103 104 int dram_init_banksize(void) 105 { 106 fdtdec_setup_memory_banksize(); 107 108 return 0; 109 } 110 111 /* KSZ8041NL/RNL */ 112 #define PHY_CONTROL1 0x1E 113 #define PHY_LED_MODE 0xC0000 114 #define PHY_LED_MODE_ACK 0x4000 115 int board_phy_config(struct phy_device *phydev) 116 { 117 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 118 ret &= ~PHY_LED_MODE; 119 ret |= PHY_LED_MODE_ACK; 120 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 121 122 return 0; 123 } 124 125 void reset_cpu(ulong addr) 126 { 127 struct udevice *dev; 128 const u8 pmic_bus = 2; 129 const u8 pmic_addr = 0x58; 130 u8 data; 131 int ret; 132 133 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 134 if (ret) 135 hang(); 136 137 ret = dm_i2c_read(dev, 0x13, &data, 1); 138 if (ret) 139 hang(); 140 141 data |= BIT(1); 142 143 ret = dm_i2c_write(dev, 0x13, &data, 1); 144 if (ret) 145 hang(); 146 } 147 148 enum env_location env_get_location(enum env_operation op, int prio) 149 { 150 const u32 load_magic = 0xb33fc0de; 151 152 /* Block environment access if loaded using JTAG */ 153 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && 154 (op != ENVOP_INIT)) 155 return ENVL_UNKNOWN; 156 157 if (prio) 158 return ENVL_UNKNOWN; 159 160 return ENVL_SPI_FLASH; 161 } 162