1 /* 2 * board/renesas/lager/lager.c 3 * This file is lager board support. 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0 9 */ 10 11 #include <common.h> 12 #include <environment.h> 13 #include <malloc.h> 14 #include <netdev.h> 15 #include <dm.h> 16 #include <dm/platform_data/serial_sh.h> 17 #include <asm/processor.h> 18 #include <asm/mach-types.h> 19 #include <asm/io.h> 20 #include <linux/errno.h> 21 #include <asm/arch/sys_proto.h> 22 #include <asm/gpio.h> 23 #include <asm/arch/rmobile.h> 24 #include <asm/arch/rcar-mstp.h> 25 #include <asm/arch/mmc.h> 26 #include <asm/arch/sh_sdhi.h> 27 #include <miiphy.h> 28 #include <i2c.h> 29 #include <mmc.h> 30 #include "qos.h" 31 32 DECLARE_GLOBAL_DATA_PTR; 33 34 #define CLK2MHZ(clk) (clk / 1000 / 1000) 35 void s_init(void) 36 { 37 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 38 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 39 40 /* Watchdog init */ 41 writel(0xA5A5A500, &rwdt->rwtcsra); 42 writel(0xA5A5A500, &swdt->swtcsra); 43 44 /* CPU frequency setting. Set to 1.4GHz */ 45 if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { 46 u32 stat = 0; 47 u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) 48 << PLL0_STC_BIT; 49 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 50 51 do { 52 stat = readl(PLLECR) & PLL0ST; 53 } while (stat == 0x0); 54 } 55 56 /* QoS(Quality-of-Service) Init */ 57 qos_init(); 58 } 59 60 #define TMU0_MSTP125 (1 << 25) 61 #define SCIF0_MSTP721 (1 << 21) 62 #define ETHER_MSTP813 (1 << 13) 63 #define MMC1_MSTP305 (1 << 5) 64 65 #define MSTPSR3 0xE6150048 66 #define SMSTPCR3 0xE615013C 67 #define SDHI0_MSTP314 (1 << 14) 68 #define SDHI1_MSTP313 (1 << 13) 69 #define SDHI2_MSTP312 (1 << 12) 70 71 #define SD2CKCR 0xE6150078 72 #define SD2_97500KHZ 0x7 73 74 int board_early_init_f(void) 75 { 76 /* TMU0 */ 77 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 78 /* SCIF0 */ 79 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); 80 /* ETHER */ 81 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 82 /* eMMC */ 83 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305); 84 /* SDHI0, 2 */ 85 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); 86 87 /* 88 * SD0 clock is set to 97.5MHz by default. 89 * Set SD2 to the 97.5MHz as well. 90 */ 91 writel(SD2_97500KHZ, SD2CKCR); 92 93 return 0; 94 } 95 96 DECLARE_GLOBAL_DATA_PTR; 97 int board_init(void) 98 { 99 /* adress of boot parameters */ 100 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 101 102 /* Init PFC controller */ 103 r8a7790_pinmux_init(); 104 105 /* ETHER Enable */ 106 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 107 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 108 gpio_request(GPIO_FN_ETH_RXD0, NULL); 109 gpio_request(GPIO_FN_ETH_RXD1, NULL); 110 gpio_request(GPIO_FN_ETH_LINK, NULL); 111 gpio_request(GPIO_FN_ETH_REF_CLK, NULL); 112 gpio_request(GPIO_FN_ETH_MDIO, NULL); 113 gpio_request(GPIO_FN_ETH_TXD1, NULL); 114 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 115 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 116 gpio_request(GPIO_FN_ETH_TXD0, NULL); 117 gpio_request(GPIO_FN_ETH_MDC, NULL); 118 gpio_request(GPIO_FN_IRQ0, NULL); 119 120 gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ 121 gpio_direction_output(GPIO_GP_5_31, 0); 122 mdelay(20); 123 gpio_set_value(GPIO_GP_5_31, 1); 124 udelay(1); 125 126 return 0; 127 } 128 129 #define CXR24 0xEE7003C0 /* MAC address high register */ 130 #define CXR25 0xEE7003C8 /* MAC address low register */ 131 int board_eth_init(bd_t *bis) 132 { 133 int ret = -ENODEV; 134 135 #ifdef CONFIG_SH_ETHER 136 u32 val; 137 unsigned char enetaddr[6]; 138 139 ret = sh_eth_initialize(bis); 140 if (!eth_env_get_enetaddr("ethaddr", enetaddr)) 141 return ret; 142 143 /* Set Mac address */ 144 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 145 enetaddr[2] << 8 | enetaddr[3]; 146 writel(val, CXR24); 147 148 val = enetaddr[4] << 8 | enetaddr[5]; 149 writel(val, CXR25); 150 151 #endif 152 153 return ret; 154 } 155 156 /* lager has KSZ8041NL/RNL */ 157 #define PHY_CONTROL1 0x1E 158 #define PHY_LED_MODE 0xC0000 159 #define PHY_LED_MODE_ACK 0x4000 160 int board_phy_config(struct phy_device *phydev) 161 { 162 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 163 ret &= ~PHY_LED_MODE; 164 ret |= PHY_LED_MODE_ACK; 165 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 166 167 return 0; 168 } 169 170 int board_mmc_init(bd_t *bis) 171 { 172 int ret = -ENODEV; 173 174 #ifdef CONFIG_SH_MMCIF 175 gpio_request(GPIO_FN_MMC1_D0, NULL); 176 gpio_request(GPIO_FN_MMC1_D1, NULL); 177 gpio_request(GPIO_FN_MMC1_D2, NULL); 178 gpio_request(GPIO_FN_MMC1_D3, NULL); 179 gpio_request(GPIO_FN_MMC1_D4, NULL); 180 gpio_request(GPIO_FN_MMC1_D5, NULL); 181 gpio_request(GPIO_FN_MMC1_D6, NULL); 182 gpio_request(GPIO_FN_MMC1_D7, NULL); 183 gpio_request(GPIO_FN_MMC1_CLK, NULL); 184 gpio_request(GPIO_FN_MMC1_CMD, NULL); 185 186 ret = mmcif_mmc_init(); 187 #endif 188 189 #ifdef CONFIG_SH_SDHI 190 gpio_request(GPIO_FN_SD0_DAT0, NULL); 191 gpio_request(GPIO_FN_SD0_DAT1, NULL); 192 gpio_request(GPIO_FN_SD0_DAT2, NULL); 193 gpio_request(GPIO_FN_SD0_DAT3, NULL); 194 gpio_request(GPIO_FN_SD0_CLK, NULL); 195 gpio_request(GPIO_FN_SD0_CMD, NULL); 196 gpio_request(GPIO_FN_SD0_CD, NULL); 197 gpio_request(GPIO_FN_SD2_DAT0, NULL); 198 gpio_request(GPIO_FN_SD2_DAT1, NULL); 199 gpio_request(GPIO_FN_SD2_DAT2, NULL); 200 gpio_request(GPIO_FN_SD2_DAT3, NULL); 201 gpio_request(GPIO_FN_SD2_CLK, NULL); 202 gpio_request(GPIO_FN_SD2_CMD, NULL); 203 gpio_request(GPIO_FN_SD2_CD, NULL); 204 205 /* 206 * SDHI 0 207 * need JP3 set to pin-1 side on board. 208 */ 209 gpio_request(GPIO_GP_5_24, NULL); 210 gpio_request(GPIO_GP_5_29, NULL); 211 gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ 212 gpio_direction_output(GPIO_GP_5_29, 1); /* 1: 3.3V, 0: 1.8V */ 213 214 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 215 SH_SDHI_QUIRK_16BIT_BUF); 216 if (ret) 217 return ret; 218 219 /* SDHI 2 */ 220 gpio_request(GPIO_GP_5_25, NULL); 221 gpio_request(GPIO_GP_5_30, NULL); 222 gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ 223 gpio_direction_output(GPIO_GP_5_30, 1); /* 1: 3.3V, 0: 1.8V */ 224 225 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); 226 #endif 227 return ret; 228 } 229 230 231 int dram_init(void) 232 { 233 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 234 235 return 0; 236 } 237 238 const struct rmobile_sysinfo sysinfo = { 239 CONFIG_ARCH_RMOBILE_BOARD_STRING 240 }; 241 242 void reset_cpu(ulong addr) 243 { 244 u8 val; 245 246 i2c_set_bus_num(3); /* PowerIC connected to ch3 */ 247 i2c_init(400000, 0); 248 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 249 val |= 0x02; 250 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 251 } 252 253 static const struct sh_serial_platdata serial_platdata = { 254 .base = SCIF0_BASE, 255 .type = PORT_SCIF, 256 .clk = 14745600, 257 .clk_mode = EXT_CLK, 258 }; 259 260 U_BOOT_DEVICE(lager_serials) = { 261 .name = "serial_sh", 262 .platdata = &serial_platdata, 263 }; 264