1 /* 2 * board/renesas/gose/gose.c 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <dm.h> 12 #include <dm/platform_data/serial_sh.h> 13 #include <environment.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <linux/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <asm/arch/rcar-mstp.h> 22 #include <asm/arch/sh_sdhi.h> 23 #include <netdev.h> 24 #include <miiphy.h> 25 #include <i2c.h> 26 #include "qos.h" 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 #define CLK2MHZ(clk) (clk / 1000 / 1000) 31 void s_init(void) 32 { 33 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 34 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 35 u32 stc; 36 37 /* Watchdog init */ 38 writel(0xA5A5A500, &rwdt->rwtcsra); 39 writel(0xA5A5A500, &swdt->swtcsra); 40 41 /* CPU frequency setting. Set to 1.5GHz */ 42 stc = ((1500 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_BIT; 43 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); 44 45 /* QoS */ 46 qos_init(); 47 } 48 49 #define TMU0_MSTP125 BIT(25) 50 51 #define SD1CKCR 0xE6150078 52 #define SD2CKCR 0xE615026C 53 #define SD_97500KHZ 0x7 54 55 int board_early_init_f(void) 56 { 57 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 58 59 /* 60 * SD0 clock is set to 97.5MHz by default. 61 * Set SD1 and SD2 to the 97.5MHz as well. 62 */ 63 writel(SD_97500KHZ, SD1CKCR); 64 writel(SD_97500KHZ, SD2CKCR); 65 66 return 0; 67 } 68 69 #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ 70 71 int board_init(void) 72 { 73 /* adress of boot parameters */ 74 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 75 76 /* Force ethernet PHY out of reset */ 77 gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 78 gpio_direction_output(ETHERNET_PHY_RESET, 0); 79 mdelay(10); 80 gpio_direction_output(ETHERNET_PHY_RESET, 1); 81 82 return 0; 83 } 84 85 int dram_init(void) 86 { 87 if (fdtdec_setup_memory_size() != 0) 88 return -EINVAL; 89 90 return 0; 91 } 92 93 int dram_init_banksize(void) 94 { 95 fdtdec_setup_memory_banksize(); 96 97 return 0; 98 } 99 100 /* KSZ8041RNLI */ 101 #define PHY_CONTROL1 0x1E 102 #define PHY_LED_MODE 0xC0000 103 #define PHY_LED_MODE_ACK 0x4000 104 int board_phy_config(struct phy_device *phydev) 105 { 106 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 107 ret &= ~PHY_LED_MODE; 108 ret |= PHY_LED_MODE_ACK; 109 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 110 111 return 0; 112 } 113 114 void reset_cpu(ulong addr) 115 { 116 struct udevice *dev; 117 const u8 pmic_bus = 6; 118 const u8 pmic_addr = 0x58; 119 u8 data; 120 int ret; 121 122 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 123 if (ret) 124 hang(); 125 126 ret = dm_i2c_read(dev, 0x13, &data, 1); 127 if (ret) 128 hang(); 129 130 data |= BIT(1); 131 132 ret = dm_i2c_write(dev, 0x13, &data, 1); 133 if (ret) 134 hang(); 135 } 136 137 enum env_location env_get_location(enum env_operation op, int prio) 138 { 139 const u32 load_magic = 0xb33fc0de; 140 141 /* Block environment access if loaded using JTAG */ 142 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && 143 (op != ENVOP_INIT)) 144 return ENVL_UNKNOWN; 145 146 if (prio) 147 return ENVL_UNKNOWN; 148 149 return ENVL_SPI_FLASH; 150 } 151