1 /* 2 * board/renesas/alt/alt.c 3 * 4 * Copyright (C) 2014, 2015 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <dm.h> 12 #include <dm/platform_data/serial_sh.h> 13 #include <environment.h> 14 #include <asm/processor.h> 15 #include <asm/mach-types.h> 16 #include <asm/io.h> 17 #include <linux/errno.h> 18 #include <asm/arch/sys_proto.h> 19 #include <asm/gpio.h> 20 #include <asm/arch/rmobile.h> 21 #include <asm/arch/rcar-mstp.h> 22 #include <asm/arch/mmc.h> 23 #include <asm/arch/sh_sdhi.h> 24 #include <netdev.h> 25 #include <miiphy.h> 26 #include <i2c.h> 27 #include <div64.h> 28 #include "qos.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define CLK2MHZ(clk) (clk / 1000 / 1000) 33 void s_init(void) 34 { 35 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 36 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 37 38 /* Watchdog init */ 39 writel(0xA5A5A500, &rwdt->rwtcsra); 40 writel(0xA5A5A500, &swdt->swtcsra); 41 42 /* QoS */ 43 qos_init(); 44 } 45 46 #define TMU0_MSTP125 BIT(25) 47 #define MMC0_MSTP315 BIT(15) 48 49 #define SD1CKCR 0xE6150078 50 #define SD_97500KHZ 0x7 51 52 int board_early_init_f(void) 53 { 54 /* TMU */ 55 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 56 57 /* Set SD1 to the 97.5MHz */ 58 writel(SD_97500KHZ, SD1CKCR); 59 60 return 0; 61 } 62 63 #define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */ 64 65 int board_init(void) 66 { 67 /* adress of boot parameters */ 68 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 69 70 /* Force ethernet PHY out of reset */ 71 gpio_request(ETHERNET_PHY_RESET, "phy_reset"); 72 gpio_direction_output(ETHERNET_PHY_RESET, 0); 73 mdelay(20); 74 gpio_direction_output(ETHERNET_PHY_RESET, 1); 75 udelay(1); 76 77 return 0; 78 } 79 80 int dram_init(void) 81 { 82 if (fdtdec_setup_memory_size() != 0) 83 return -EINVAL; 84 85 return 0; 86 } 87 88 int dram_init_banksize(void) 89 { 90 fdtdec_setup_memory_banksize(); 91 92 return 0; 93 } 94 95 /* KSZ8041RNLI */ 96 #define PHY_CONTROL1 0x1E 97 #define PHY_LED_MODE 0xC0000 98 #define PHY_LED_MODE_ACK 0x4000 99 int board_phy_config(struct phy_device *phydev) 100 { 101 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); 102 ret &= ~PHY_LED_MODE; 103 ret |= PHY_LED_MODE_ACK; 104 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); 105 106 return 0; 107 } 108 109 void reset_cpu(ulong addr) 110 { 111 struct udevice *dev; 112 const u8 pmic_bus = 1; 113 const u8 pmic_addr = 0x58; 114 u8 data; 115 int ret; 116 117 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); 118 if (ret) 119 hang(); 120 121 ret = dm_i2c_read(dev, 0x13, &data, 1); 122 if (ret) 123 hang(); 124 125 data |= BIT(1); 126 127 ret = dm_i2c_write(dev, 0x13, &data, 1); 128 if (ret) 129 hang(); 130 } 131 132 enum env_location env_get_location(enum env_operation op, int prio) 133 { 134 const u32 load_magic = 0xb33fc0de; 135 136 /* Block environment access if loaded using JTAG */ 137 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && 138 (op != ENVOP_INIT)) 139 return ENVL_UNKNOWN; 140 141 if (prio) 142 return ENVL_UNKNOWN; 143 144 return ENVL_SPI_FLASH; 145 } 146