183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2127f9ae5SJean-Christophe PLAGNIOL-VILLARD /*
3127f9ae5SJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2008
4127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Grazvydas Ignotas <notasas@gmail.com>
5127f9ae5SJean-Christophe PLAGNIOL-VILLARD *
6127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
7127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Richard Woodruff <r-woodruff2@ti.com>
8127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Syed Mohammed Khasim <khasim@ti.com>
9127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Sunil Kumar <sunilsaini05@gmail.com>
10127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Shashi Ranjan <shashiranjanmca05@gmail.com>
11127f9ae5SJean-Christophe PLAGNIOL-VILLARD *
12127f9ae5SJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2004-2008
13127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Texas Instruments, <www.ti.com>
14127f9ae5SJean-Christophe PLAGNIOL-VILLARD */
15127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <common.h>
16*8a86152dSGrazvydas Ignotas #include <dm.h>
17*8a86152dSGrazvydas Ignotas #include <ns16550.h>
18127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <twl4030.h>
19127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h>
207cad446bSGrazvydas Ignotas #include <asm/gpio.h>
2186c5c544STom Rini #include <asm/arch/mmc_host_def.h>
22127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/mux.h>
23080a46eaSAneesh V #include <asm/arch/gpio.h>
24127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/sys_proto.h>
25127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include <asm/mach-types.h>
26127f9ae5SJean-Christophe PLAGNIOL-VILLARD #include "pandora.h"
27127f9ae5SJean-Christophe PLAGNIOL-VILLARD
2829565326SJohn Rigby DECLARE_GLOBAL_DATA_PTR;
2929565326SJohn Rigby
305246d01eSGrazvydas Ignotas #define TWL4030_BB_CFG_BBCHEN (1 << 4)
315246d01eSGrazvydas Ignotas #define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2)
325246d01eSGrazvydas Ignotas #define TWL4030_BB_CFG_BBISEL_500UA 2
335246d01eSGrazvydas Ignotas
347cad446bSGrazvydas Ignotas #define CONTROL_WKUP_CTRL 0x48002a5c
357cad446bSGrazvydas Ignotas #define GPIO_IO_PWRDNZ (1 << 6)
367cad446bSGrazvydas Ignotas #define PBIASLITEVMODE1 (1 << 8)
377cad446bSGrazvydas Ignotas
38*8a86152dSGrazvydas Ignotas static const struct ns16550_platdata pandora_serial = {
39*8a86152dSGrazvydas Ignotas .base = OMAP34XX_UART3,
40*8a86152dSGrazvydas Ignotas .reg_shift = 2,
41*8a86152dSGrazvydas Ignotas .clock = V_NS16550_CLK,
42*8a86152dSGrazvydas Ignotas .fcr = UART_FCR_DEFVAL,
43*8a86152dSGrazvydas Ignotas };
44*8a86152dSGrazvydas Ignotas
45*8a86152dSGrazvydas Ignotas U_BOOT_DEVICE(pandora_uart) = {
46*8a86152dSGrazvydas Ignotas "ns16550_serial",
47*8a86152dSGrazvydas Ignotas &pandora_serial
48*8a86152dSGrazvydas Ignotas };
49*8a86152dSGrazvydas Ignotas
50127f9ae5SJean-Christophe PLAGNIOL-VILLARD /*
51127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Routine: board_init
52127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Description: Early hardware init.
53127f9ae5SJean-Christophe PLAGNIOL-VILLARD */
board_init(void)54127f9ae5SJean-Christophe PLAGNIOL-VILLARD int board_init(void)
55127f9ae5SJean-Christophe PLAGNIOL-VILLARD {
56127f9ae5SJean-Christophe PLAGNIOL-VILLARD gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
57127f9ae5SJean-Christophe PLAGNIOL-VILLARD /* board id for Linux */
58127f9ae5SJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
59127f9ae5SJean-Christophe PLAGNIOL-VILLARD /* boot param addr */
60127f9ae5SJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
61127f9ae5SJean-Christophe PLAGNIOL-VILLARD
62127f9ae5SJean-Christophe PLAGNIOL-VILLARD return 0;
63127f9ae5SJean-Christophe PLAGNIOL-VILLARD }
64127f9ae5SJean-Christophe PLAGNIOL-VILLARD
set_output_gpio(unsigned int gpio,int value)657cad446bSGrazvydas Ignotas static void set_output_gpio(unsigned int gpio, int value)
667cad446bSGrazvydas Ignotas {
677cad446bSGrazvydas Ignotas int ret;
687cad446bSGrazvydas Ignotas
697cad446bSGrazvydas Ignotas ret = gpio_request(gpio, "");
707cad446bSGrazvydas Ignotas if (ret != 0) {
717cad446bSGrazvydas Ignotas printf("could not request GPIO %u\n", gpio);
727cad446bSGrazvydas Ignotas return;
737cad446bSGrazvydas Ignotas }
747cad446bSGrazvydas Ignotas ret = gpio_direction_output(gpio, value);
757cad446bSGrazvydas Ignotas if (ret != 0)
767cad446bSGrazvydas Ignotas printf("could not set GPIO %u to %d\n", gpio, value);
777cad446bSGrazvydas Ignotas }
787cad446bSGrazvydas Ignotas
79127f9ae5SJean-Christophe PLAGNIOL-VILLARD /*
80127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Routine: misc_init_r
81127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Description: Configure board specific parts
82127f9ae5SJean-Christophe PLAGNIOL-VILLARD */
misc_init_r(void)83127f9ae5SJean-Christophe PLAGNIOL-VILLARD int misc_init_r(void)
84127f9ae5SJean-Christophe PLAGNIOL-VILLARD {
857cad446bSGrazvydas Ignotas t2_t *t2_base = (t2_t *)T2_BASE;
867cad446bSGrazvydas Ignotas u32 pbias_lite;
87127f9ae5SJean-Christophe PLAGNIOL-VILLARD
88ead39d7aSGrazvydas Ignotas twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
89127f9ae5SJean-Christophe PLAGNIOL-VILLARD
907cad446bSGrazvydas Ignotas /* set up dual-voltage GPIOs to 1.8V */
917cad446bSGrazvydas Ignotas pbias_lite = readl(&t2_base->pbias_lite);
927cad446bSGrazvydas Ignotas pbias_lite &= ~PBIASLITEVMODE1;
937cad446bSGrazvydas Ignotas pbias_lite |= PBIASLITEPWRDNZ1;
947cad446bSGrazvydas Ignotas writel(pbias_lite, &t2_base->pbias_lite);
957cad446bSGrazvydas Ignotas if (get_cpu_family() == CPU_OMAP36XX)
967cad446bSGrazvydas Ignotas writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
977cad446bSGrazvydas Ignotas CONTROL_WKUP_CTRL);
98127f9ae5SJean-Christophe PLAGNIOL-VILLARD
997cad446bSGrazvydas Ignotas /* make sure audio and BT chips are in powerdown state */
1007cad446bSGrazvydas Ignotas set_output_gpio(14, 0);
1017cad446bSGrazvydas Ignotas set_output_gpio(15, 0);
1027cad446bSGrazvydas Ignotas set_output_gpio(118, 0);
1037cad446bSGrazvydas Ignotas
1047cad446bSGrazvydas Ignotas /* enable USB supply */
1057cad446bSGrazvydas Ignotas set_output_gpio(164, 1);
1067cad446bSGrazvydas Ignotas
1077cad446bSGrazvydas Ignotas /* wifi needs a short pulse to enter powersave state */
1087cad446bSGrazvydas Ignotas set_output_gpio(23, 1);
1097cad446bSGrazvydas Ignotas udelay(5000);
1107cad446bSGrazvydas Ignotas gpio_direction_output(23, 0);
111127f9ae5SJean-Christophe PLAGNIOL-VILLARD
1125246d01eSGrazvydas Ignotas /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
1135246d01eSGrazvydas Ignotas twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
1140208aaf6SNishanth Menon TWL4030_PM_RECEIVER_BB_CFG,
1155246d01eSGrazvydas Ignotas TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
1160208aaf6SNishanth Menon TWL4030_BB_CFG_BBISEL_500UA);
1175246d01eSGrazvydas Ignotas
118679f82c3SPaul Kocialkowski omap_die_id_display();
119127f9ae5SJean-Christophe PLAGNIOL-VILLARD
120127f9ae5SJean-Christophe PLAGNIOL-VILLARD return 0;
121127f9ae5SJean-Christophe PLAGNIOL-VILLARD }
122127f9ae5SJean-Christophe PLAGNIOL-VILLARD
123127f9ae5SJean-Christophe PLAGNIOL-VILLARD /*
124127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Routine: set_muxconf_regs
125127f9ae5SJean-Christophe PLAGNIOL-VILLARD * Description: Setting up the configuration Mux registers specific to the
126127f9ae5SJean-Christophe PLAGNIOL-VILLARD * hardware. Many pins need to be moved from protect to primary
127127f9ae5SJean-Christophe PLAGNIOL-VILLARD * mode.
128127f9ae5SJean-Christophe PLAGNIOL-VILLARD */
set_muxconf_regs(void)129127f9ae5SJean-Christophe PLAGNIOL-VILLARD void set_muxconf_regs(void)
130127f9ae5SJean-Christophe PLAGNIOL-VILLARD {
131127f9ae5SJean-Christophe PLAGNIOL-VILLARD MUX_PANDORA();
13210cd73bfSGrazvydas Ignotas if (get_cpu_family() == CPU_OMAP36XX) {
13310cd73bfSGrazvydas Ignotas MUX_PANDORA_3730();
13410cd73bfSGrazvydas Ignotas }
135127f9ae5SJean-Christophe PLAGNIOL-VILLARD }
13686c5c544STom Rini
1374aa2ba3aSMasahiro Yamada #ifdef CONFIG_MMC
board_mmc_init(bd_t * bis)13886c5c544STom Rini int board_mmc_init(bd_t *bis)
13986c5c544STom Rini {
140e3913f56SNikita Kiryanov return omap_mmc_init(0, 0, 0, -1, -1);
14186c5c544STom Rini }
142aac5450eSPaul Kocialkowski
board_mmc_power_init(void)143aac5450eSPaul Kocialkowski void board_mmc_power_init(void)
144aac5450eSPaul Kocialkowski {
145aac5450eSPaul Kocialkowski twl4030_power_mmc_init(0);
146aac5450eSPaul Kocialkowski }
14786c5c544STom Rini #endif
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