1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2fe5d488fSArun Bharadwaj /* 3fe5d488fSArun Bharadwaj * Maintainer : Steve Sakoman <steve@sakoman.com> 4fe5d488fSArun Bharadwaj * 5fe5d488fSArun Bharadwaj * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by 6fe5d488fSArun Bharadwaj * Richard Woodruff <r-woodruff2@ti.com> 7fe5d488fSArun Bharadwaj * Syed Mohammed Khasim <khasim@ti.com> 8fe5d488fSArun Bharadwaj * Sunil Kumar <sunilsaini05@gmail.com> 9fe5d488fSArun Bharadwaj * Shashi Ranjan <shashiranjanmca05@gmail.com> 10fe5d488fSArun Bharadwaj * 11fe5d488fSArun Bharadwaj * (C) Copyright 2004-2008 12fe5d488fSArun Bharadwaj * Texas Instruments, <www.ti.com> 13fe5d488fSArun Bharadwaj */ 14fe5d488fSArun Bharadwaj #include <asm/io.h> 15fe5d488fSArun Bharadwaj #include <asm/arch/mem.h> 16fe5d488fSArun Bharadwaj #include <asm/arch/sys_proto.h> 17fe5d488fSArun Bharadwaj #include "overo.h" 18fe5d488fSArun Bharadwaj 19fe5d488fSArun Bharadwaj /* 20fe5d488fSArun Bharadwaj * Routine: get_board_mem_timings 21fe5d488fSArun Bharadwaj * Description: If we use SPL then there is no x-loader nor config header 22fe5d488fSArun Bharadwaj * so we have to setup the DDR timings ourself on both banks. 23fe5d488fSArun Bharadwaj */ get_board_mem_timings(struct board_sdrc_timings * timings)24fe5d488fSArun Bharadwajvoid get_board_mem_timings(struct board_sdrc_timings *timings) 25fe5d488fSArun Bharadwaj { 26fe5d488fSArun Bharadwaj timings->mr = MICRON_V_MR_165; 27fe5d488fSArun Bharadwaj switch (get_board_revision()) { 28fe5d488fSArun Bharadwaj case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ 29fe5d488fSArun Bharadwaj timings->mcfg = MICRON_V_MCFG_165(256 << 20); 30fe5d488fSArun Bharadwaj timings->ctrla = MICRON_V_ACTIMA_165; 31fe5d488fSArun Bharadwaj timings->ctrlb = MICRON_V_ACTIMB_165; 32fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 33fe5d488fSArun Bharadwaj break; 34fe5d488fSArun Bharadwaj case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ 35fe5d488fSArun Bharadwaj case REVISION_4: 36fe5d488fSArun Bharadwaj timings->mcfg = MICRON_V_MCFG_200(256 << 20); 37fe5d488fSArun Bharadwaj timings->ctrla = MICRON_V_ACTIMA_200; 38fe5d488fSArun Bharadwaj timings->ctrlb = MICRON_V_ACTIMB_200; 39fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 40fe5d488fSArun Bharadwaj break; 41fe5d488fSArun Bharadwaj case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ 42fe5d488fSArun Bharadwaj timings->mcfg = HYNIX_V_MCFG_200(256 << 20); 43fe5d488fSArun Bharadwaj timings->ctrla = HYNIX_V_ACTIMA_200; 44fe5d488fSArun Bharadwaj timings->ctrlb = HYNIX_V_ACTIMB_200; 45fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 46fe5d488fSArun Bharadwaj break; 47fe5d488fSArun Bharadwaj case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */ 48fe5d488fSArun Bharadwaj timings->mcfg = MCFG(512 << 20, 15); 49fe5d488fSArun Bharadwaj timings->ctrla = MICRON_V_ACTIMA_200; 50fe5d488fSArun Bharadwaj timings->ctrlb = MICRON_V_ACTIMB_200; 51fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; 52fe5d488fSArun Bharadwaj break; 53fe5d488fSArun Bharadwaj default: 54fe5d488fSArun Bharadwaj timings->mcfg = MICRON_V_MCFG_165(128 << 20); 55fe5d488fSArun Bharadwaj timings->ctrla = MICRON_V_ACTIMA_165; 56fe5d488fSArun Bharadwaj timings->ctrlb = MICRON_V_ACTIMB_165; 57fe5d488fSArun Bharadwaj timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; 58fe5d488fSArun Bharadwaj } 59fe5d488fSArun Bharadwaj } 60