1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2f7dc4ac3STom Warren /* 3f7dc4ac3STom Warren * (C) Copyright 2013-2014 4f7dc4ac3STom Warren * NVIDIA Corporation <www.nvidia.com> 5f7dc4ac3STom Warren */ 6f7dc4ac3STom Warren 7f7dc4ac3STom Warren #include <common.h> 8f7dc4ac3STom Warren #include <asm/arch/gpio.h> 9f7dc4ac3STom Warren #include <asm/arch/pinmux.h> 10f7dc4ac3STom Warren #include "pinmux-config-venice2.h" 11f7dc4ac3STom Warren 12f7dc4ac3STom Warren /* 13f7dc4ac3STom Warren * Routine: pinmux_init 14f7dc4ac3STom Warren * Description: Do individual peripheral pinmux configs 15f7dc4ac3STom Warren */ pinmux_init(void)16f7dc4ac3STom Warrenvoid pinmux_init(void) 17f7dc4ac3STom Warren { 182eba87a3SStephen Warren pinmux_set_tristate_input_clamping(); 19f7dc4ac3STom Warren 202eba87a3SStephen Warren gpio_config_table(venice2_gpio_inits, 212eba87a3SStephen Warren ARRAY_SIZE(venice2_gpio_inits)); 22f7dc4ac3STom Warren 232eba87a3SStephen Warren pinmux_config_pingrp_table(venice2_pingrps, 242eba87a3SStephen Warren ARRAY_SIZE(venice2_pingrps)); 25f7dc4ac3STom Warren 262eba87a3SStephen Warren pinmux_config_drvgrp_table(venice2_drvgrps, 272eba87a3SStephen Warren ARRAY_SIZE(venice2_drvgrps)); 28f7dc4ac3STom Warren } 29