1*f7dc4ac3STom Warren /* 2*f7dc4ac3STom Warren * (C) Copyright 2013 3*f7dc4ac3STom Warren * NVIDIA Corporation <www.nvidia.com> 4*f7dc4ac3STom Warren * 5*f7dc4ac3STom Warren * SPDX-License-Identifier: GPL-2.0+ 6*f7dc4ac3STom Warren */ 7*f7dc4ac3STom Warren 8*f7dc4ac3STom Warren /* AS3722-PMIC-specific early init regs */ 9*f7dc4ac3STom Warren 10*f7dc4ac3STom Warren #define AS3722_I2C_ADDR 0x80 11*f7dc4ac3STom Warren 12*f7dc4ac3STom Warren #define AS3722_SD0VOLTAGE_REG 0x00 /* CPU */ 13*f7dc4ac3STom Warren #define AS3722_SD1VOLTAGE_REG 0x01 /* CORE, already set by OTP */ 14*f7dc4ac3STom Warren #define AS3722_SD6VOLTAGE_REG 0x06 /* GPU */ 15*f7dc4ac3STom Warren #define AS3722_SDCONTROL_REG 0x4D 16*f7dc4ac3STom Warren 17*f7dc4ac3STom Warren #define AS3722_LDO2VOLTAGE_REG 0x12 /* VPP_FUSE */ 18*f7dc4ac3STom Warren #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */ 19*f7dc4ac3STom Warren #define AS3722_LDCONTROL_REG 0x4E 20*f7dc4ac3STom Warren 21*f7dc4ac3STom Warren #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG) 22*f7dc4ac3STom Warren #define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) 23*f7dc4ac3STom Warren 24*f7dc4ac3STom Warren #define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) 25*f7dc4ac3STom Warren #define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) 26*f7dc4ac3STom Warren 27*f7dc4ac3STom Warren #define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) 28*f7dc4ac3STom Warren #define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) 29*f7dc4ac3STom Warren 30*f7dc4ac3STom Warren #define AS3722_LDO2CONTROL_DATA (0x0400 | AS3722_LDCONTROL_REG) 31*f7dc4ac3STom Warren #define AS3722_LDO2VOLTAGE_DATA (0x1000 | AS3722_LDO2VOLTAGE_REG) 32*f7dc4ac3STom Warren 33*f7dc4ac3STom Warren #define AS3722_LDO6CONTROL_DATA (0x4000 | AS3722_LDCONTROL_REG) 34*f7dc4ac3STom Warren #define AS3722_LDO6VOLTAGE_DATA (0x3F00 | AS3722_LDO6VOLTAGE_REG) 35*f7dc4ac3STom Warren 36*f7dc4ac3STom Warren #define I2C_SEND_2_BYTES 0x0A02 37*f7dc4ac3STom Warren 38*f7dc4ac3STom Warren void pmic_enable_cpu_vdd(void); 39