1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2e04bfdacSStephen Warren /*
3e04bfdacSStephen Warren * (C) Copyright 2014
4e04bfdacSStephen Warren * NVIDIA Corporation <www.nvidia.com>
5e04bfdacSStephen Warren */
6e04bfdacSStephen Warren
7e04bfdacSStephen Warren #include <common.h>
8e3f44f5cSSimon Glass #include <dm.h>
96e2fca94SThierry Reding #include <power/as3722.h>
10e3f44f5cSSimon Glass #include <power/pmic.h>
116e2fca94SThierry Reding
129348532fSStephen Warren #include <asm/arch/gpio.h>
13e04bfdacSStephen Warren #include <asm/arch/pinmux.h>
146e2fca94SThierry Reding
15e04bfdacSStephen Warren #include "pinmux-config-jetson-tk1.h"
16e04bfdacSStephen Warren
17e04bfdacSStephen Warren /*
18e04bfdacSStephen Warren * Routine: pinmux_init
19e04bfdacSStephen Warren * Description: Do individual peripheral pinmux configs
20e04bfdacSStephen Warren */
pinmux_init(void)21e04bfdacSStephen Warren void pinmux_init(void)
22e04bfdacSStephen Warren {
23c1fe92feSStephen Warren pinmux_clear_tristate_input_clamping();
244ff213b8SStephen Warren
259348532fSStephen Warren gpio_config_table(jetson_tk1_gpio_inits,
269348532fSStephen Warren ARRAY_SIZE(jetson_tk1_gpio_inits));
279348532fSStephen Warren
28e04bfdacSStephen Warren pinmux_config_pingrp_table(jetson_tk1_pingrps,
29e04bfdacSStephen Warren ARRAY_SIZE(jetson_tk1_pingrps));
30e04bfdacSStephen Warren
31e04bfdacSStephen Warren pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
32e04bfdacSStephen Warren ARRAY_SIZE(jetson_tk1_drvgrps));
33bbca7108SStephen Warren
34bbca7108SStephen Warren pinmux_config_mipipadctrlgrp_table(jetson_tk1_mipipadctrlgrps,
35bbca7108SStephen Warren ARRAY_SIZE(jetson_tk1_mipipadctrlgrps));
36e04bfdacSStephen Warren }
376e2fca94SThierry Reding
386e2fca94SThierry Reding #ifdef CONFIG_PCI_TEGRA
39e3f44f5cSSimon Glass /* TODO: Convert to driver model */
as3722_sd_enable(struct udevice * pmic,unsigned int sd)40e3f44f5cSSimon Glass static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
416e2fca94SThierry Reding {
426e2fca94SThierry Reding int err;
436e2fca94SThierry Reding
44e3f44f5cSSimon Glass if (sd > 6)
45e3f44f5cSSimon Glass return -EINVAL;
46e3f44f5cSSimon Glass
47e3f44f5cSSimon Glass err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
486e2fca94SThierry Reding if (err) {
499b643e31SMasahiro Yamada pr_err("failed to update SD control register: %d", err);
506e2fca94SThierry Reding return err;
516e2fca94SThierry Reding }
526e2fca94SThierry Reding
53e3f44f5cSSimon Glass return 0;
546e2fca94SThierry Reding }
556e2fca94SThierry Reding
tegra_pcie_board_init(void)56e3f44f5cSSimon Glass int tegra_pcie_board_init(void)
57e3f44f5cSSimon Glass {
58e3f44f5cSSimon Glass struct udevice *dev;
59e3f44f5cSSimon Glass int ret;
60e3f44f5cSSimon Glass
61e3f44f5cSSimon Glass ret = uclass_get_device_by_driver(UCLASS_PMIC,
62e3f44f5cSSimon Glass DM_GET_DRIVER(pmic_as3722), &dev);
63e3f44f5cSSimon Glass if (ret) {
64e3f44f5cSSimon Glass debug("%s: Failed to find PMIC\n", __func__);
65e3f44f5cSSimon Glass return ret;
66e3f44f5cSSimon Glass }
67e3f44f5cSSimon Glass
68e3f44f5cSSimon Glass ret = as3722_sd_enable(dev, 4);
69e3f44f5cSSimon Glass if (ret < 0) {
709b643e31SMasahiro Yamada pr_err("failed to enable SD4: %d\n", ret);
71e3f44f5cSSimon Glass return ret;
72e3f44f5cSSimon Glass }
73e3f44f5cSSimon Glass
74e3f44f5cSSimon Glass ret = as3722_sd_set_voltage(dev, 4, 0x24);
75e3f44f5cSSimon Glass if (ret < 0) {
769b643e31SMasahiro Yamada pr_err("failed to set SD4 voltage: %d\n", ret);
77e3f44f5cSSimon Glass return ret;
786e2fca94SThierry Reding }
796e2fca94SThierry Reding
806e2fca94SThierry Reding return 0;
816e2fca94SThierry Reding }
826e2fca94SThierry Reding #endif /* PCI */
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