xref: /openbmc/u-boot/board/mscc/ocelot/ocelot.c (revision aff66f22d6eeb27c6329c0a3c1ebc52914c8affa)
16787c1ecSGregory CLEMENT // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
26787c1ecSGregory CLEMENT /*
36787c1ecSGregory CLEMENT  * Copyright (c) 2018 Microsemi Corporation
46787c1ecSGregory CLEMENT  */
56787c1ecSGregory CLEMENT 
66787c1ecSGregory CLEMENT #include <common.h>
76787c1ecSGregory CLEMENT #include <asm/io.h>
86787c1ecSGregory CLEMENT #include <asm/addrspace.h>
96787c1ecSGregory CLEMENT #include <asm/types.h>
106787c1ecSGregory CLEMENT #include <environment.h>
116787c1ecSGregory CLEMENT #include <spi.h>
124deb0963SLars Povlsen #include <led.h>
13*2f8d0677SGregory CLEMENT #include <wait_bit.h>
146787c1ecSGregory CLEMENT 
156787c1ecSGregory CLEMENT DECLARE_GLOBAL_DATA_PTR;
166787c1ecSGregory CLEMENT 
17e9f1492bSLars Povlsen enum {
18e9f1492bSLars Povlsen 	BOARD_TYPE_PCB120 = 0xAABBCC00,
19e9f1492bSLars Povlsen 	BOARD_TYPE_PCB123,
20e9f1492bSLars Povlsen };
216787c1ecSGregory CLEMENT 
mscc_switch_reset(bool enter)22*2f8d0677SGregory CLEMENT void mscc_switch_reset(bool enter)
23*2f8d0677SGregory CLEMENT {
24*2f8d0677SGregory CLEMENT 	/* Nasty workaround to avoid GPIO19 (DDR!) being reset */
25*2f8d0677SGregory CLEMENT 	mscc_gpio_set_alternate(19, 2);
26*2f8d0677SGregory CLEMENT 
27*2f8d0677SGregory CLEMENT 	debug("applying SwC reset\n");
28*2f8d0677SGregory CLEMENT 
29*2f8d0677SGregory CLEMENT 	writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
30*2f8d0677SGregory CLEMENT 	writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
31*2f8d0677SGregory CLEMENT 
32*2f8d0677SGregory CLEMENT 	if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
33*2f8d0677SGregory CLEMENT 			      PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
34*2f8d0677SGregory CLEMENT 		pr_err("Tiemout while waiting for switch reset\n");
35*2f8d0677SGregory CLEMENT 
36*2f8d0677SGregory CLEMENT 	/*
37*2f8d0677SGregory CLEMENT 	 * Reset GPIO19 mode back as regular GPIO, output, high (DDR
38*2f8d0677SGregory CLEMENT 	 * not reset) (Order is important)
39*2f8d0677SGregory CLEMENT 	 */
40*2f8d0677SGregory CLEMENT 	setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
41*2f8d0677SGregory CLEMENT 	writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
42*2f8d0677SGregory CLEMENT 	mscc_gpio_set_alternate(19, 0);
43*2f8d0677SGregory CLEMENT }
44*2f8d0677SGregory CLEMENT 
board_debug_uart_init(void)456787c1ecSGregory CLEMENT void board_debug_uart_init(void)
466787c1ecSGregory CLEMENT {
476787c1ecSGregory CLEMENT 	/* too early for the pinctrl driver, so configure the UART pins here */
48e9f1492bSLars Povlsen 	mscc_gpio_set_alternate(6, 1);
49e9f1492bSLars Povlsen 	mscc_gpio_set_alternate(7, 1);
506787c1ecSGregory CLEMENT }
516787c1ecSGregory CLEMENT 
board_early_init_r(void)526787c1ecSGregory CLEMENT int board_early_init_r(void)
536787c1ecSGregory CLEMENT {
546787c1ecSGregory CLEMENT 	/* Prepare SPI controller to be used in master mode */
556787c1ecSGregory CLEMENT 	writel(0, BASE_CFG + ICPU_SW_MODE);
566787c1ecSGregory CLEMENT 	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
576787c1ecSGregory CLEMENT 			ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
586787c1ecSGregory CLEMENT 			ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
596787c1ecSGregory CLEMENT 
606787c1ecSGregory CLEMENT 	/* Address of boot parameters */
616787c1ecSGregory CLEMENT 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
624deb0963SLars Povlsen 
634deb0963SLars Povlsen 	/* LED setup */
644deb0963SLars Povlsen 	if (IS_ENABLED(CONFIG_LED))
654deb0963SLars Povlsen 		led_default_state();
664deb0963SLars Povlsen 
676787c1ecSGregory CLEMENT 	return 0;
686787c1ecSGregory CLEMENT }
69e9f1492bSLars Povlsen 
do_board_detect(void)70e9f1492bSLars Povlsen static void do_board_detect(void)
71e9f1492bSLars Povlsen {
72e9f1492bSLars Povlsen 	u16 dummy = 0;
73e9f1492bSLars Povlsen 
74e9f1492bSLars Povlsen 	/* Enable MIIM */
75e9f1492bSLars Povlsen 	mscc_gpio_set_alternate(14, 1);
76e9f1492bSLars Povlsen 	mscc_gpio_set_alternate(15, 1);
77e9f1492bSLars Povlsen 	if (mscc_phy_rd(1, 0, 0, &dummy) == 0)
78e9f1492bSLars Povlsen 		gd->board_type = BOARD_TYPE_PCB120;
79e9f1492bSLars Povlsen 	else
80e9f1492bSLars Povlsen 		gd->board_type = BOARD_TYPE_PCB123;
81e9f1492bSLars Povlsen }
82e9f1492bSLars Povlsen 
83e9f1492bSLars Povlsen #if defined(CONFIG_MULTI_DTB_FIT)
board_fit_config_name_match(const char * name)84e9f1492bSLars Povlsen int board_fit_config_name_match(const char *name)
85e9f1492bSLars Povlsen {
86e9f1492bSLars Povlsen 	if (gd->board_type == BOARD_TYPE_PCB120 &&
87e9f1492bSLars Povlsen 	    strcmp(name, "ocelot_pcb120") == 0)
88e9f1492bSLars Povlsen 		return 0;
89e9f1492bSLars Povlsen 
90e9f1492bSLars Povlsen 	if (gd->board_type == BOARD_TYPE_PCB123 &&
91e9f1492bSLars Povlsen 	    strcmp(name, "ocelot_pcb123") == 0)
92e9f1492bSLars Povlsen 		return 0;
93e9f1492bSLars Povlsen 
94e9f1492bSLars Povlsen 	return -1;
95e9f1492bSLars Povlsen }
96e9f1492bSLars Povlsen #endif
97e9f1492bSLars Povlsen 
98e9f1492bSLars Povlsen #if defined(CONFIG_DTB_RESELECT)
embedded_dtb_select(void)99e9f1492bSLars Povlsen int embedded_dtb_select(void)
100e9f1492bSLars Povlsen {
101e9f1492bSLars Povlsen 	do_board_detect();
102e9f1492bSLars Povlsen 	fdtdec_setup();
103e9f1492bSLars Povlsen 
104e9f1492bSLars Povlsen 	return 0;
105e9f1492bSLars Povlsen }
106e9f1492bSLars Povlsen #endif
107