1*50752790SStefan Roese /* 2*50752790SStefan Roese * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering 3*50752790SStefan Roese * 4*50752790SStefan Roese * Copyright (C) 2006 Micronas GmbH 5*50752790SStefan Roese * 6*50752790SStefan Roese * This program is free software; you can redistribute it and/or 7*50752790SStefan Roese * modify it under the terms of the GNU General Public License as 8*50752790SStefan Roese * published by the Free Software Foundation; either version 2 of 9*50752790SStefan Roese * the License, or (at your option) any later version. 10*50752790SStefan Roese * 11*50752790SStefan Roese * This program is distributed in the hope that it will be useful, 12*50752790SStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*50752790SStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*50752790SStefan Roese * GNU General Public License for more details. 15*50752790SStefan Roese * 16*50752790SStefan Roese * You should have received a copy of the GNU General Public License 17*50752790SStefan Roese * along with this program; if not, write to the Free Software 18*50752790SStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19*50752790SStefan Roese * MA 02111-1307 USA 20*50752790SStefan Roese */ 21*50752790SStefan Roese 22*50752790SStefan Roese #ifndef _DCGU_H 23*50752790SStefan Roese #define _DCGU_H 24*50752790SStefan Roese 25*50752790SStefan Roese enum dcgu_switch { 26*50752790SStefan Roese DCGU_SWITCH_OFF, /* Switch off */ 27*50752790SStefan Roese DCGU_SWITCH_ON /* Switch on */ 28*50752790SStefan Roese }; 29*50752790SStefan Roese 30*50752790SStefan Roese enum dcgu_hw_module { 31*50752790SStefan Roese DCGU_HW_MODULE_DCGU, /* Selects digital clock gen. unit */ 32*50752790SStefan Roese 33*50752790SStefan Roese DCGU_HW_MODULE_MIC32_SCI, /* Selects MIC32 SoC interface */ 34*50752790SStefan Roese DCGU_HW_MODULE_SCI, /* Selects SCI target agent port modules*/ 35*50752790SStefan Roese 36*50752790SStefan Roese DCGU_HW_MODULE_MR1, /* Selects first MPEG reader module */ 37*50752790SStefan Roese DCGU_HW_MODULE_MR2, /* Selects second MPEG reader module */ 38*50752790SStefan Roese DCGU_HW_MODULE_MVD, /* Selects MPEG video decoder module */ 39*50752790SStefan Roese DCGU_HW_MODULE_DVP, /* Selects dig video processing module */ 40*50752790SStefan Roese DCGU_HW_MODULE_CVE, /* Selects color video encoder module */ 41*50752790SStefan Roese DCGU_HW_MODULE_VID_ENC, /* Selects video encoder module */ 42*50752790SStefan Roese 43*50752790SStefan Roese DCGU_HW_MODULE_SSI_S, /* Selects slave sync serial interface */ 44*50752790SStefan Roese DCGU_HW_MODULE_SSI_M, /* Selects master sync serial interface */ 45*50752790SStefan Roese 46*50752790SStefan Roese DCGU_HW_MODULE_GA, /* Selects graphics accelerator module */ 47*50752790SStefan Roese DCGU_HW_MODULE_DGPU, /* Selects digital graphics processing */ 48*50752790SStefan Roese 49*50752790SStefan Roese DCGU_HW_MODULE_UART_1, /* Selects first UART module */ 50*50752790SStefan Roese DCGU_HW_MODULE_UART_2, /* Selects second UART module */ 51*50752790SStefan Roese 52*50752790SStefan Roese DCGU_HW_MODULE_AD, /* Selects audio decoder module */ 53*50752790SStefan Roese DCGU_HW_MODULE_ABP_DTV, /* Selects audio baseband processing */ 54*50752790SStefan Roese DCGU_HW_MODULE_ABP_SCC, /* Selects audio base band processor SCC*/ 55*50752790SStefan Roese DCGU_HW_MODULE_SPDIF, /* Selects sony philips digital interf. */ 56*50752790SStefan Roese 57*50752790SStefan Roese DCGU_HW_MODULE_TSIO, /* Selects trasnport stream input/output*/ 58*50752790SStefan Roese DCGU_HW_MODULE_TSD, /* Selects trasnport stream decoder */ 59*50752790SStefan Roese DCGU_HW_MODULE_TSD_KEY, /* Selects trasnport stream decoder key */ 60*50752790SStefan Roese 61*50752790SStefan Roese DCGU_HW_MODULE_USBH, /* Selects USB hub module */ 62*50752790SStefan Roese DCGU_HW_MODULE_USB_PLL, /* Selects USB phase locked loop module */ 63*50752790SStefan Roese DCGU_HW_MODULE_USB_60, /* Selects USB 60 module */ 64*50752790SStefan Roese DCGU_HW_MODULE_USB_24, /* Selects USB 24 module */ 65*50752790SStefan Roese 66*50752790SStefan Roese DCGU_HW_MODULE_PERI, /* Selects all mod connected to clkperi20*/ 67*50752790SStefan Roese DCGU_HW_MODULE_WDT, /* Selects wtg timer mod con to clkperi20*/ 68*50752790SStefan Roese DCGU_HW_MODULE_I2C1, /* Selects first I2C mod con to clkperi20*/ 69*50752790SStefan Roese DCGU_HW_MODULE_I2C2, /* Selects 2nd I2C mod con to clkperi20 */ 70*50752790SStefan Roese DCGU_HW_MODULE_GPIO1, /* Selects gpio module 1 */ 71*50752790SStefan Roese DCGU_HW_MODULE_GPIO2, /* Selects gpio module 2 */ 72*50752790SStefan Roese 73*50752790SStefan Roese DCGU_HW_MODULE_GPT, /* Selects gpt mod connected to clkperi20*/ 74*50752790SStefan Roese DCGU_HW_MODULE_PWM, /* Selects pwm mod connected to clkperi20*/ 75*50752790SStefan Roese 76*50752790SStefan Roese DCGU_HW_MODULE_MPC, /* Selects multi purpose cipher module */ 77*50752790SStefan Roese DCGU_HW_MODULE_MPC_KEY, /* Selects multi purpose cipher key */ 78*50752790SStefan Roese 79*50752790SStefan Roese DCGU_HW_MODULE_COM, /* Selects COM unit module */ 80*50752790SStefan Roese DCGU_HW_MODULE_VCTY_CORE, /* Selects VCT-Y core module */ 81*50752790SStefan Roese DCGU_HW_MODULE_FWSRAM, /* Selects firmware SRAM module */ 82*50752790SStefan Roese 83*50752790SStefan Roese DCGU_HW_MODULE_EBI, /* Selects external bus interface module*/ 84*50752790SStefan Roese DCGU_HW_MODULE_I2S, /* Selects integrated interchip sound */ 85*50752790SStefan Roese DCGU_HW_MODULE_MSMC, /* Selects memory stick and mmc module */ 86*50752790SStefan Roese DCGU_HW_MODULE_SMC, /* Selects smartcard interface module */ 87*50752790SStefan Roese 88*50752790SStefan Roese DCGU_HW_MODULE_IRQC, /* Selects interrupt C module */ 89*50752790SStefan Roese DCGU_HW_MODULE_TOP, /* Selects top level pinmux module */ 90*50752790SStefan Roese DCGU_HW_MODULE_SRAM, /* Selects SRAM module */ 91*50752790SStefan Roese DCGU_HW_MODULE_EIC, /* Selects External Interrupt controller*/ 92*50752790SStefan Roese DCGU_HW_MODULE_CPU, /* Selects CPU subsystem module */ 93*50752790SStefan Roese DCGU_HW_MODULE_SCC, /* Selects SCC module */ 94*50752790SStefan Roese DCGU_HW_MODULE_MM, /* Selects Memory Manager module */ 95*50752790SStefan Roese DCGU_HW_MODULE_BCU, /* Selects Buffer Configuration Unit */ 96*50752790SStefan Roese DCGU_HW_MODULE_FH, /* Selects FIFO Handler module */ 97*50752790SStefan Roese DCGU_HW_MODULE_IMU, /* Selects Interrupt Management Unit */ 98*50752790SStefan Roese DCGU_HW_MODULE_MDU, /* Selects MCI Debug Unit module */ 99*50752790SStefan Roese DCGU_HW_MODULE_SI2OCP /* Selects Standard Interface to OCP bridge*/ 100*50752790SStefan Roese }; 101*50752790SStefan Roese 102*50752790SStefan Roese union dcgu_clk_en1 { 103*50752790SStefan Roese u32 reg; 104*50752790SStefan Roese struct { 105*50752790SStefan Roese u32 res1:8; /* reserved */ 106*50752790SStefan Roese u32 en_clkmsmc:1; /* Enable bit for clkmsmc (#) */ 107*50752790SStefan Roese u32 en_clkssi_s:1; /* Enable bit for clkssi_s (#) */ 108*50752790SStefan Roese u32 en_clkssi_m:1; /* Enable bit for clkssi_m (#) */ 109*50752790SStefan Roese u32 en_clksmc:1; /* Enable bit for clksmc (#) */ 110*50752790SStefan Roese u32 en_clkebi:1; /* Enable bit for clkebi (#) */ 111*50752790SStefan Roese u32 en_usbpll:1; /* Enable bit for the USB PLL */ 112*50752790SStefan Roese u32 en_clkusb60:1; /* Enable bit for clkusb60 (#) */ 113*50752790SStefan Roese u32 en_clkusb24:1; /* Enable bit for clkusb24 (#) */ 114*50752790SStefan Roese u32 en_clkuart2:1; /* Enable bit for clkuart2 (#) */ 115*50752790SStefan Roese u32 en_clkuart1:1; /* Enable bit for clkuart1 (#) */ 116*50752790SStefan Roese u32 en_clkperi20:1; /* Enable bit for clkperi20 (#) */ 117*50752790SStefan Roese u32 res2:3; /* reserved */ 118*50752790SStefan Roese u32 en_clk_i2s_dly:1; /* Enable bit for clk_scc_abp */ 119*50752790SStefan Roese u32 en_clk_scc_abp:1; /* Enable bit for clk_scc_abp */ 120*50752790SStefan Roese u32 en_clk_dtv_spdo:1; /* Enable bit for clk_dtv_spdo */ 121*50752790SStefan Roese u32 en_clkad:1; /* Enable bit for clkad (#) */ 122*50752790SStefan Roese u32 en_clkmvd:1; /* Enable bit for clkmvd (#) */ 123*50752790SStefan Roese u32 en_clktsd:1; /* Enable bit for clktsd (#) */ 124*50752790SStefan Roese u32 en_clkga:1; /* Enable bit for clkga (#) */ 125*50752790SStefan Roese u32 en_clkdvp:1; /* Enable bit for clkdvp (#) */ 126*50752790SStefan Roese u32 en_clkmr2:1; /* Enable bit for clkmr2 (#) */ 127*50752790SStefan Roese u32 en_clkmr1:1; /* Enable bit for clkmr1 (#) */ 128*50752790SStefan Roese } bits; 129*50752790SStefan Roese }; 130*50752790SStefan Roese 131*50752790SStefan Roese union dcgu_clk_en2 { 132*50752790SStefan Roese u32 reg; 133*50752790SStefan Roese struct { 134*50752790SStefan Roese u32 res1:31; /* reserved */ 135*50752790SStefan Roese u32 en_clkcpu:1; /* Enable bit for clkcpu */ 136*50752790SStefan Roese } bits; 137*50752790SStefan Roese }; 138*50752790SStefan Roese 139*50752790SStefan Roese union dcgu_reset_unit1 { 140*50752790SStefan Roese u32 reg; 141*50752790SStefan Roese struct { 142*50752790SStefan Roese u32 res1:1; 143*50752790SStefan Roese u32 swreset_clkmsmc:1; 144*50752790SStefan Roese u32 swreset_clkssi_s:1; 145*50752790SStefan Roese u32 swreset_clkssi_m:1; 146*50752790SStefan Roese u32 swreset_clksmc:1; 147*50752790SStefan Roese u32 swreset_clkebi:1; 148*50752790SStefan Roese u32 swreset_clkusb60:1; 149*50752790SStefan Roese u32 swreset_clkusb24:1; 150*50752790SStefan Roese u32 swreset_clkuart2:1; 151*50752790SStefan Roese u32 swreset_clkuart1:1; 152*50752790SStefan Roese u32 swreset_pwm:1; 153*50752790SStefan Roese u32 swreset_gpt:1; 154*50752790SStefan Roese u32 swreset_i2c2:1; 155*50752790SStefan Roese u32 swreset_i2c1:1; 156*50752790SStefan Roese u32 swreset_gpio2:1; 157*50752790SStefan Roese u32 swreset_gpio1:1; 158*50752790SStefan Roese u32 swreset_clkcpu:1; 159*50752790SStefan Roese u32 res2:2; 160*50752790SStefan Roese u32 swreset_clk_i2s_dly:1; 161*50752790SStefan Roese u32 swreset_clk_scc_abp:1; 162*50752790SStefan Roese u32 swreset_clk_dtv_spdo:1; 163*50752790SStefan Roese u32 swreset_clkad:1; 164*50752790SStefan Roese u32 swreset_clkmvd:1; 165*50752790SStefan Roese u32 swreset_clktsd:1; 166*50752790SStefan Roese u32 swreset_clktsio:1; 167*50752790SStefan Roese u32 swreset_clkga:1; 168*50752790SStefan Roese u32 swreset_clkmpc:1; 169*50752790SStefan Roese u32 swreset_clkcve:1; 170*50752790SStefan Roese u32 swreset_clkdvp:1; 171*50752790SStefan Roese u32 swreset_clkmr2:1; 172*50752790SStefan Roese u32 swreset_clkmr1:1; 173*50752790SStefan Roese } bits; 174*50752790SStefan Roese }; 175*50752790SStefan Roese 176*50752790SStefan Roese int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup); 177*50752790SStefan Roese int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup); 178*50752790SStefan Roese 179*50752790SStefan Roese #endif /* _DCGU_H */ 180