1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
250752790SStefan Roese /*
350752790SStefan Roese * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
450752790SStefan Roese *
550752790SStefan Roese * Original Author Guenter Gebhardt
650752790SStefan Roese * Copyright (C) 2006 Micronas GmbH
750752790SStefan Roese */
850752790SStefan Roese
950752790SStefan Roese #include <common.h>
101221ce45SMasahiro Yamada #include <linux/errno.h>
1150752790SStefan Roese
1250752790SStefan Roese #include "vct.h"
1350752790SStefan Roese
dcgu_set_clk_switch(enum dcgu_hw_module module,enum dcgu_switch setup)1450752790SStefan Roese int dcgu_set_clk_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
1550752790SStefan Roese {
1650752790SStefan Roese u32 enable;
1750752790SStefan Roese union dcgu_clk_en1 en1;
1850752790SStefan Roese union dcgu_clk_en2 en2;
1950752790SStefan Roese
2050752790SStefan Roese switch (setup) {
2150752790SStefan Roese case DCGU_SWITCH_ON:
2250752790SStefan Roese enable = 1;
2350752790SStefan Roese break;
2450752790SStefan Roese case DCGU_SWITCH_OFF:
2550752790SStefan Roese enable = 0;
2650752790SStefan Roese break;
2750752790SStefan Roese default:
2850752790SStefan Roese printf("%s:%i:Invalid clock switch: %i\n", __FILE__, __LINE__,
2950752790SStefan Roese setup);
3050752790SStefan Roese return -EINVAL;
3150752790SStefan Roese }
3250752790SStefan Roese
3350752790SStefan Roese if (module == DCGU_HW_MODULE_CPU)
3450752790SStefan Roese en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
3550752790SStefan Roese else
3650752790SStefan Roese en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
3750752790SStefan Roese
3850752790SStefan Roese switch (module) {
3950752790SStefan Roese case DCGU_HW_MODULE_MSMC:
4050752790SStefan Roese en1.bits.en_clkmsmc = enable;
4150752790SStefan Roese break;
4250752790SStefan Roese case DCGU_HW_MODULE_SSI_S:
4350752790SStefan Roese en1.bits.en_clkssi_s = enable;
4450752790SStefan Roese break;
4550752790SStefan Roese case DCGU_HW_MODULE_SSI_M:
4650752790SStefan Roese en1.bits.en_clkssi_m = enable;
4750752790SStefan Roese break;
4850752790SStefan Roese case DCGU_HW_MODULE_SMC:
4950752790SStefan Roese en1.bits.en_clksmc = enable;
5050752790SStefan Roese break;
5150752790SStefan Roese case DCGU_HW_MODULE_EBI:
5250752790SStefan Roese en1.bits.en_clkebi = enable;
5350752790SStefan Roese break;
5450752790SStefan Roese case DCGU_HW_MODULE_USB_PLL:
5550752790SStefan Roese en1.bits.en_usbpll = enable;
5650752790SStefan Roese break;
5750752790SStefan Roese case DCGU_HW_MODULE_USB_60:
5850752790SStefan Roese en1.bits.en_clkusb60 = enable;
5950752790SStefan Roese break;
6050752790SStefan Roese case DCGU_HW_MODULE_USB_24:
6150752790SStefan Roese en1.bits.en_clkusb24 = enable;
6250752790SStefan Roese break;
6350752790SStefan Roese case DCGU_HW_MODULE_UART_2:
6450752790SStefan Roese en1.bits.en_clkuart2 = enable;
6550752790SStefan Roese break;
6650752790SStefan Roese case DCGU_HW_MODULE_UART_1:
6750752790SStefan Roese en1.bits.en_clkuart1 = enable;
6850752790SStefan Roese break;
6950752790SStefan Roese case DCGU_HW_MODULE_PERI:
7050752790SStefan Roese en1.bits.en_clkperi20 = enable;
7150752790SStefan Roese break;
7250752790SStefan Roese case DCGU_HW_MODULE_CPU:
7350752790SStefan Roese en2.bits.en_clkcpu = enable;
7450752790SStefan Roese break;
7550752790SStefan Roese case DCGU_HW_MODULE_I2S:
7650752790SStefan Roese en1.bits.en_clk_i2s_dly = enable;
7750752790SStefan Roese break;
7850752790SStefan Roese case DCGU_HW_MODULE_ABP_SCC:
7950752790SStefan Roese en1.bits.en_clk_scc_abp = enable;
8050752790SStefan Roese break;
8150752790SStefan Roese case DCGU_HW_MODULE_SPDIF:
8250752790SStefan Roese en1.bits.en_clk_dtv_spdo = enable;
8350752790SStefan Roese break;
8450752790SStefan Roese case DCGU_HW_MODULE_AD:
8550752790SStefan Roese en1.bits.en_clkad = enable;
8650752790SStefan Roese break;
8750752790SStefan Roese case DCGU_HW_MODULE_MVD:
8850752790SStefan Roese en1.bits.en_clkmvd = enable;
8950752790SStefan Roese break;
9050752790SStefan Roese case DCGU_HW_MODULE_TSD:
9150752790SStefan Roese en1.bits.en_clktsd = enable;
9250752790SStefan Roese break;
9350752790SStefan Roese case DCGU_HW_MODULE_GA:
9450752790SStefan Roese en1.bits.en_clkga = enable;
9550752790SStefan Roese break;
9650752790SStefan Roese case DCGU_HW_MODULE_DVP:
9750752790SStefan Roese en1.bits.en_clkdvp = enable;
9850752790SStefan Roese break;
9950752790SStefan Roese case DCGU_HW_MODULE_MR2:
10050752790SStefan Roese en1.bits.en_clkmr2 = enable;
10150752790SStefan Roese break;
10250752790SStefan Roese case DCGU_HW_MODULE_MR1:
10350752790SStefan Roese en1.bits.en_clkmr1 = enable;
10450752790SStefan Roese break;
10550752790SStefan Roese default:
10650752790SStefan Roese printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
10750752790SStefan Roese __LINE__, module);
10850752790SStefan Roese return -EINVAL;
10950752790SStefan Roese }
11050752790SStefan Roese
11150752790SStefan Roese /*
11250752790SStefan Roese * The reg_read() following the reg_write() below forces the write to
11350752790SStefan Roese * be really done on the bus.
11450752790SStefan Roese * Otherwise the clock may not be switched on when this API function
11550752790SStefan Roese * returns, which may cause an bus error if a registers of the hardware
11650752790SStefan Roese * module connected to the clock is accessed.
11750752790SStefan Roese */
11850752790SStefan Roese if (module == DCGU_HW_MODULE_CPU) {
11950752790SStefan Roese reg_write(DCGU_CLK_EN2(DCGU_BASE), en2.reg);
12050752790SStefan Roese en2.reg = reg_read(DCGU_CLK_EN2(DCGU_BASE));
12150752790SStefan Roese } else {
12250752790SStefan Roese reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg);
12350752790SStefan Roese en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE));
12450752790SStefan Roese }
12550752790SStefan Roese
12650752790SStefan Roese return 0;
12750752790SStefan Roese }
12850752790SStefan Roese
dcgu_set_reset_switch(enum dcgu_hw_module module,enum dcgu_switch setup)12950752790SStefan Roese int dcgu_set_reset_switch(enum dcgu_hw_module module, enum dcgu_switch setup)
13050752790SStefan Roese {
13150752790SStefan Roese union dcgu_reset_unit1 val;
13250752790SStefan Roese u32 enable;
13350752790SStefan Roese
13450752790SStefan Roese switch (setup) {
13550752790SStefan Roese case DCGU_SWITCH_ON:
13650752790SStefan Roese enable = 1;
13750752790SStefan Roese break;
13850752790SStefan Roese case DCGU_SWITCH_OFF:
13950752790SStefan Roese enable = 0;
14050752790SStefan Roese break;
14150752790SStefan Roese default:
14250752790SStefan Roese printf("%s:%i:Invalid reset switch: %i\n", __FILE__, __LINE__,
14350752790SStefan Roese setup);
14450752790SStefan Roese return -EINVAL;
14550752790SStefan Roese }
14650752790SStefan Roese
14750752790SStefan Roese val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));
14850752790SStefan Roese switch (module) {
14950752790SStefan Roese case DCGU_HW_MODULE_MSMC:
15050752790SStefan Roese val.bits.swreset_clkmsmc = enable;
15150752790SStefan Roese break;
15250752790SStefan Roese case DCGU_HW_MODULE_SSI_S:
15350752790SStefan Roese val.bits.swreset_clkssi_s = enable;
15450752790SStefan Roese break;
15550752790SStefan Roese case DCGU_HW_MODULE_SSI_M:
15650752790SStefan Roese val.bits.swreset_clkssi_m = enable;
15750752790SStefan Roese break;
15850752790SStefan Roese case DCGU_HW_MODULE_SMC:
15950752790SStefan Roese val.bits.swreset_clksmc = enable;
16050752790SStefan Roese break;
16150752790SStefan Roese case DCGU_HW_MODULE_EBI:
16250752790SStefan Roese val.bits.swreset_clkebi = enable;
16350752790SStefan Roese break;
16450752790SStefan Roese case DCGU_HW_MODULE_USB_60:
16550752790SStefan Roese val.bits.swreset_clkusb60 = enable;
16650752790SStefan Roese break;
16750752790SStefan Roese case DCGU_HW_MODULE_USB_24:
16850752790SStefan Roese val.bits.swreset_clkusb24 = enable;
16950752790SStefan Roese break;
17050752790SStefan Roese case DCGU_HW_MODULE_UART_2:
17150752790SStefan Roese val.bits.swreset_clkuart2 = enable;
17250752790SStefan Roese break;
17350752790SStefan Roese case DCGU_HW_MODULE_UART_1:
17450752790SStefan Roese val.bits.swreset_clkuart1 = enable;
17550752790SStefan Roese break;
17650752790SStefan Roese case DCGU_HW_MODULE_PWM:
17750752790SStefan Roese val.bits.swreset_pwm = enable;
17850752790SStefan Roese break;
17950752790SStefan Roese case DCGU_HW_MODULE_GPT:
18050752790SStefan Roese val.bits.swreset_gpt = enable;
18150752790SStefan Roese break;
18250752790SStefan Roese case DCGU_HW_MODULE_I2C2:
18350752790SStefan Roese val.bits.swreset_i2c2 = enable;
18450752790SStefan Roese break;
18550752790SStefan Roese case DCGU_HW_MODULE_I2C1:
18650752790SStefan Roese val.bits.swreset_i2c1 = enable;
18750752790SStefan Roese break;
18850752790SStefan Roese case DCGU_HW_MODULE_GPIO2:
18950752790SStefan Roese val.bits.swreset_gpio2 = enable;
19050752790SStefan Roese break;
19150752790SStefan Roese case DCGU_HW_MODULE_GPIO1:
19250752790SStefan Roese val.bits.swreset_gpio1 = enable;
19350752790SStefan Roese break;
19450752790SStefan Roese case DCGU_HW_MODULE_CPU:
19550752790SStefan Roese val.bits.swreset_clkcpu = enable;
19650752790SStefan Roese break;
19750752790SStefan Roese case DCGU_HW_MODULE_I2S:
19850752790SStefan Roese val.bits.swreset_clk_i2s_dly = enable;
19950752790SStefan Roese break;
20050752790SStefan Roese case DCGU_HW_MODULE_ABP_SCC:
20150752790SStefan Roese val.bits.swreset_clk_scc_abp = enable;
20250752790SStefan Roese break;
20350752790SStefan Roese case DCGU_HW_MODULE_SPDIF:
20450752790SStefan Roese val.bits.swreset_clk_dtv_spdo = enable;
20550752790SStefan Roese break;
20650752790SStefan Roese case DCGU_HW_MODULE_AD:
20750752790SStefan Roese val.bits.swreset_clkad = enable;
20850752790SStefan Roese break;
20950752790SStefan Roese case DCGU_HW_MODULE_MVD:
21050752790SStefan Roese val.bits.swreset_clkmvd = enable;
21150752790SStefan Roese break;
21250752790SStefan Roese case DCGU_HW_MODULE_TSD:
21350752790SStefan Roese val.bits.swreset_clktsd = enable;
21450752790SStefan Roese break;
21550752790SStefan Roese case DCGU_HW_MODULE_TSIO:
21650752790SStefan Roese val.bits.swreset_clktsio = enable;
21750752790SStefan Roese break;
21850752790SStefan Roese case DCGU_HW_MODULE_GA:
21950752790SStefan Roese val.bits.swreset_clkga = enable;
22050752790SStefan Roese break;
22150752790SStefan Roese case DCGU_HW_MODULE_MPC:
22250752790SStefan Roese val.bits.swreset_clkmpc = enable;
22350752790SStefan Roese break;
22450752790SStefan Roese case DCGU_HW_MODULE_CVE:
22550752790SStefan Roese val.bits.swreset_clkcve = enable;
22650752790SStefan Roese break;
22750752790SStefan Roese case DCGU_HW_MODULE_DVP:
22850752790SStefan Roese val.bits.swreset_clkdvp = enable;
22950752790SStefan Roese break;
23050752790SStefan Roese case DCGU_HW_MODULE_MR2:
23150752790SStefan Roese val.bits.swreset_clkmr2 = enable;
23250752790SStefan Roese break;
23350752790SStefan Roese case DCGU_HW_MODULE_MR1:
23450752790SStefan Roese val.bits.swreset_clkmr1 = enable;
23550752790SStefan Roese break;
23650752790SStefan Roese default:
23750752790SStefan Roese printf("%s:%i:Invalid hardware module: %i\n", __FILE__,
23850752790SStefan Roese __LINE__, module);
23950752790SStefan Roese return -EINVAL;
24050752790SStefan Roese }
24150752790SStefan Roese reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);
24250752790SStefan Roese
24350752790SStefan Roese return 0;
24450752790SStefan Roese }
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