1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2350f3ac5SJean-Christophe PLAGNIOL-VILLARD /*
3350f3ac5SJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2004-2008
4350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Texas Instruments, <www.ti.com>
5350f3ac5SJean-Christophe PLAGNIOL-VILLARD *
6350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Author :
7350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Nishanth Menon <nm@ti.com>
8350f3ac5SJean-Christophe PLAGNIOL-VILLARD *
9350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Derived from Beagle Board and 3430 SDP code by
10350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Sunil Kumar <sunilsaini05@gmail.com>
11350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Shashi Ranjan <shashiranjanmca05@gmail.com>
12350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Richard Woodruff <r-woodruff2@ti.com>
13350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Syed Mohammed Khasim <khasim@ti.com>
14350f3ac5SJean-Christophe PLAGNIOL-VILLARD *
15350f3ac5SJean-Christophe PLAGNIOL-VILLARD */
16350f3ac5SJean-Christophe PLAGNIOL-VILLARD #include <common.h>
17b3f4ca11SSimon Glass #include <dm.h>
189925f1dbSAlex Kiernan #include <environment.h>
19b3f4ca11SSimon Glass #include <ns16550.h>
201ab70f6fSBen Warren #include <netdev.h>
21350f3ac5SJean-Christophe PLAGNIOL-VILLARD #include <twl4030.h>
220568dd06SLadislav Michl #include <linux/mtd/omap_gpmc.h>
23350f3ac5SJean-Christophe PLAGNIOL-VILLARD #include <asm/io.h>
24c2800b16SNishanth Menon #include <asm/arch/mem.h>
25d6906cb8STom Rini #include <asm/arch/mmc_host_def.h>
26350f3ac5SJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/mux.h>
27350f3ac5SJean-Christophe PLAGNIOL-VILLARD #include <asm/arch/sys_proto.h>
28350f3ac5SJean-Christophe PLAGNIOL-VILLARD #include <asm/mach-types.h>
29350f3ac5SJean-Christophe PLAGNIOL-VILLARD #include "zoom1.h"
30350f3ac5SJean-Christophe PLAGNIOL-VILLARD
3129565326SJohn Rigby DECLARE_GLOBAL_DATA_PTR;
3229565326SJohn Rigby
330568dd06SLadislav Michl /*
340568dd06SLadislav Michl * gpmc_cfg is initialized by gpmc_init and we use it here.
350568dd06SLadislav Michl * GPMC definitions for Ethenet Controller LAN9211
360568dd06SLadislav Michl */
37c2800b16SNishanth Menon static const u32 gpmc_lab_enet[] = {
38c2800b16SNishanth Menon ZOOM1_ENET_GPMC_CONF1,
39c2800b16SNishanth Menon ZOOM1_ENET_GPMC_CONF2,
40c2800b16SNishanth Menon ZOOM1_ENET_GPMC_CONF3,
41c2800b16SNishanth Menon ZOOM1_ENET_GPMC_CONF4,
42c2800b16SNishanth Menon ZOOM1_ENET_GPMC_CONF5,
43c2800b16SNishanth Menon ZOOM1_ENET_GPMC_CONF6,
44c2800b16SNishanth Menon /*CONF7- computed as params */
45c2800b16SNishanth Menon };
46c2800b16SNishanth Menon
47b3f4ca11SSimon Glass static const struct ns16550_platdata zoom1_serial = {
482f6ed3b8SAdam Ford .base = OMAP34XX_UART3,
492f6ed3b8SAdam Ford .reg_shift = 2,
5017fa0326SHeiko Schocher .clock = V_NS16550_CLK,
5117fa0326SHeiko Schocher .fcr = UART_FCR_DEFVAL,
52b3f4ca11SSimon Glass };
53b3f4ca11SSimon Glass
54b3f4ca11SSimon Glass U_BOOT_DEVICE(zoom1_uart) = {
55c7b9686dSThomas Chou "ns16550_serial",
56b3f4ca11SSimon Glass &zoom1_serial
57b3f4ca11SSimon Glass };
58b3f4ca11SSimon Glass
59350f3ac5SJean-Christophe PLAGNIOL-VILLARD /*
60350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Routine: board_init
61350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Description: Early hardware init.
62350f3ac5SJean-Christophe PLAGNIOL-VILLARD */
board_init(void)63350f3ac5SJean-Christophe PLAGNIOL-VILLARD int board_init(void)
64350f3ac5SJean-Christophe PLAGNIOL-VILLARD {
65350f3ac5SJean-Christophe PLAGNIOL-VILLARD gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
66c2800b16SNishanth Menon /* CS1 is Ethernet LAN9211 */
67c2800b16SNishanth Menon enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
68c2800b16SNishanth Menon DEBUG_BASE, GPMC_SIZE_16M);
69350f3ac5SJean-Christophe PLAGNIOL-VILLARD /* board id for Linux */
70350f3ac5SJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
71350f3ac5SJean-Christophe PLAGNIOL-VILLARD /* boot param addr */
72350f3ac5SJean-Christophe PLAGNIOL-VILLARD gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
73350f3ac5SJean-Christophe PLAGNIOL-VILLARD
74350f3ac5SJean-Christophe PLAGNIOL-VILLARD return 0;
75350f3ac5SJean-Christophe PLAGNIOL-VILLARD }
76350f3ac5SJean-Christophe PLAGNIOL-VILLARD
77350f3ac5SJean-Christophe PLAGNIOL-VILLARD /*
78350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Routine: misc_init_r
79350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Description: Configure zoom board specific configurations
80350f3ac5SJean-Christophe PLAGNIOL-VILLARD */
misc_init_r(void)81350f3ac5SJean-Christophe PLAGNIOL-VILLARD int misc_init_r(void)
82350f3ac5SJean-Christophe PLAGNIOL-VILLARD {
83350f3ac5SJean-Christophe PLAGNIOL-VILLARD twl4030_power_init();
84ead39d7aSGrazvydas Ignotas twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
85679f82c3SPaul Kocialkowski omap_die_id_display();
86350f3ac5SJean-Christophe PLAGNIOL-VILLARD
87350f3ac5SJean-Christophe PLAGNIOL-VILLARD /*
88350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Board Reset
89350f3ac5SJean-Christophe PLAGNIOL-VILLARD * The board is reset by holding the red button on the
90350f3ac5SJean-Christophe PLAGNIOL-VILLARD * top right front face for eight seconds.
91350f3ac5SJean-Christophe PLAGNIOL-VILLARD */
92350f3ac5SJean-Christophe PLAGNIOL-VILLARD twl4030_power_reset_init();
93350f3ac5SJean-Christophe PLAGNIOL-VILLARD
94350f3ac5SJean-Christophe PLAGNIOL-VILLARD return 0;
95350f3ac5SJean-Christophe PLAGNIOL-VILLARD }
96350f3ac5SJean-Christophe PLAGNIOL-VILLARD
97350f3ac5SJean-Christophe PLAGNIOL-VILLARD /*
98350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Routine: set_muxconf_regs
99350f3ac5SJean-Christophe PLAGNIOL-VILLARD * Description: Setting up the configuration Mux registers specific to the
100350f3ac5SJean-Christophe PLAGNIOL-VILLARD * hardware. Many pins need to be moved from protect to primary
101350f3ac5SJean-Christophe PLAGNIOL-VILLARD * mode.
102350f3ac5SJean-Christophe PLAGNIOL-VILLARD */
set_muxconf_regs(void)103350f3ac5SJean-Christophe PLAGNIOL-VILLARD void set_muxconf_regs(void)
104350f3ac5SJean-Christophe PLAGNIOL-VILLARD {
105350f3ac5SJean-Christophe PLAGNIOL-VILLARD /* platform specific muxes */
106350f3ac5SJean-Christophe PLAGNIOL-VILLARD MUX_ZOOM1_MDK();
107350f3ac5SJean-Christophe PLAGNIOL-VILLARD }
1081ab70f6fSBen Warren
1094aa2ba3aSMasahiro Yamada #ifdef CONFIG_MMC
board_mmc_init(bd_t * bis)110d6906cb8STom Rini int board_mmc_init(bd_t *bis)
111d6906cb8STom Rini {
112e3913f56SNikita Kiryanov return omap_mmc_init(0, 0, 0, -1, -1);
113d6906cb8STom Rini }
114aac5450eSPaul Kocialkowski
board_mmc_power_init(void)115aac5450eSPaul Kocialkowski void board_mmc_power_init(void)
116aac5450eSPaul Kocialkowski {
117aac5450eSPaul Kocialkowski twl4030_power_mmc_init(0);
118aac5450eSPaul Kocialkowski }
119d6906cb8STom Rini #endif
120d6906cb8STom Rini
1211ab70f6fSBen Warren #ifdef CONFIG_CMD_NET
board_eth_init(bd_t * bis)1221ab70f6fSBen Warren int board_eth_init(bd_t *bis)
1231ab70f6fSBen Warren {
1241ab70f6fSBen Warren int rc = 0;
1259d70e772SNishanth Menon
1269d70e772SNishanth Menon #ifdef CONFIG_SMC911X
1279d70e772SNishanth Menon #define STR_ENV_ETHADDR "ethaddr"
1289d70e772SNishanth Menon
1299d70e772SNishanth Menon struct eth_device *dev;
1309d70e772SNishanth Menon uchar eth_addr[6];
1319d70e772SNishanth Menon
1329d70e772SNishanth Menon rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
13335affd7aSSimon Glass if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
1349d70e772SNishanth Menon dev = eth_get_dev_by_index(0);
1359d70e772SNishanth Menon if (dev) {
136fd1e959eSSimon Glass eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
1379d70e772SNishanth Menon } else {
1389d70e772SNishanth Menon printf("zoom1: Couldn't get eth device\n");
1399d70e772SNishanth Menon rc = -1;
1409d70e772SNishanth Menon }
1419d70e772SNishanth Menon }
1421ab70f6fSBen Warren #endif
1439d70e772SNishanth Menon
1441ab70f6fSBen Warren return rc;
1451ab70f6fSBen Warren }
1461ab70f6fSBen Warren #endif
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