1 /* 2 * Novena SPL 3 * 4 * Copyright (C) 2014 Marek Vasut <marex@denx.de> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/mx6-ddr.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/mach-imx/boot_mode.h> 18 #include <asm/mach-imx/iomux-v3.h> 19 #include <asm/mach-imx/mxc_i2c.h> 20 #include <asm/arch/crm_regs.h> 21 #include <i2c.h> 22 #include <mmc.h> 23 #include <fsl_esdhc.h> 24 #include <spl.h> 25 26 #include <asm/arch/mx6-ddr.h> 27 28 #include "novena.h" 29 30 #define UART_PAD_CTRL \ 31 (PAD_CTL_PKE | PAD_CTL_PUE | \ 32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 34 35 #define USDHC_PAD_CTRL \ 36 (PAD_CTL_PKE | PAD_CTL_PUE | \ 37 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 38 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define ENET_PAD_CTRL \ 41 (PAD_CTL_PKE | PAD_CTL_PUE | \ 42 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 43 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 44 45 #define ENET_PHY_CFG_PAD_CTRL \ 46 (PAD_CTL_PKE | PAD_CTL_PUE | \ 47 PAD_CTL_PUS_22K_UP | PAD_CTL_HYS) 48 49 #define RGMII_PAD_CTRL \ 50 (PAD_CTL_PKE | PAD_CTL_PUE | \ 51 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 52 53 #define SPI_PAD_CTRL \ 54 (PAD_CTL_HYS | \ 55 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ 56 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) 57 58 #define I2C_PAD_CTRL \ 59 (PAD_CTL_PKE | PAD_CTL_PUE | \ 60 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 61 PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \ 62 PAD_CTL_ODE) 63 64 #define BUTTON_PAD_CTRL \ 65 (PAD_CTL_PKE | PAD_CTL_PUE | \ 66 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 67 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 68 69 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 70 71 /* 72 * Audio 73 */ 74 static iomux_v3_cfg_t audio_pads[] = { 75 /* AUD_PWRON */ 76 MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), 77 }; 78 79 static void novena_spl_setup_iomux_audio(void) 80 { 81 imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads)); 82 gpio_direction_output(NOVENA_AUDIO_PWRON, 1); 83 } 84 85 /* 86 * ENET 87 */ 88 static iomux_v3_cfg_t enet_pads1[] = { 89 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 90 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 91 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), 92 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 93 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 94 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 95 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 96 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), 97 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 98 99 /* pin 35, PHY_AD2 */ 100 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 101 /* pin 32, MODE0 */ 102 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 103 /* pin 31, MODE1 */ 104 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 105 /* pin 28, MODE2 */ 106 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 107 /* pin 27, MODE3 */ 108 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 109 /* pin 33, CLK125_EN */ 110 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), 111 112 /* pin 42 PHY nRST */ 113 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), 114 }; 115 116 static iomux_v3_cfg_t enet_pads2[] = { 117 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), 118 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 119 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 120 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 121 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), 122 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), 123 }; 124 125 static void novena_spl_setup_iomux_enet(void) 126 { 127 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); 128 129 /* Assert Ethernet PHY nRST */ 130 gpio_direction_output(IMX_GPIO_NR(3, 23), 0); 131 132 /* 133 * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset 134 * de-assertion. The intention is to use weak signal drivers (pull-ups) 135 * to prevent the conflict between PHY pins becoming outputs after 136 * reset and imx6 still driving the pins. The issue is described in PHY 137 * datasheet, p.14 138 */ 139 gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */ 140 gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */ 141 gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */ 142 gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */ 143 gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */ 144 gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */ 145 146 /* Following reset timing (p.53, fig.8 from the PHY datasheet) */ 147 mdelay(10); 148 149 /* De-assert Ethernet PHY nRST */ 150 gpio_set_value(IMX_GPIO_NR(3, 23), 1); 151 152 /* PHY is now configured, connect FEC to the pads */ 153 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); 154 155 /* 156 * PHY datasheet recommends on p.53 to wait at least 100us after reset 157 * before using MII, so we enforce the delay here 158 */ 159 udelay(100); 160 } 161 162 /* 163 * FPGA 164 */ 165 static iomux_v3_cfg_t fpga_pads[] = { 166 /* FPGA_RESET_N */ 167 MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), 168 }; 169 170 static void novena_spl_setup_iomux_fpga(void) 171 { 172 imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads)); 173 gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0); 174 } 175 176 /* 177 * GPIO Button 178 */ 179 static iomux_v3_cfg_t button_pads[] = { 180 /* Debug */ 181 MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), 182 }; 183 184 static void novena_spl_setup_iomux_buttons(void) 185 { 186 imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads)); 187 } 188 189 /* 190 * I2C 191 */ 192 /* 193 * I2C1: 194 * 0x1d ... MMA7455L 195 * 0x30 ... SO-DIMM temp sensor 196 * 0x44 ... STMPE610 197 * 0x50 ... SO-DIMM ID 198 */ 199 struct i2c_pads_info i2c_pad_info0 = { 200 .scl = { 201 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, 202 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, 203 .gp = IMX_GPIO_NR(3, 21) 204 }, 205 .sda = { 206 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, 207 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, 208 .gp = IMX_GPIO_NR(3, 28) 209 } 210 }; 211 212 /* 213 * I2C2: 214 * 0x08 ... PMIC 215 * 0x3a ... HDMI DCC 216 * 0x50 ... HDMI DCC 217 */ 218 static struct i2c_pads_info i2c_pad_info1 = { 219 .scl = { 220 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, 221 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, 222 .gp = IMX_GPIO_NR(2, 30) 223 }, 224 .sda = { 225 .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, 226 .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, 227 .gp = IMX_GPIO_NR(3, 16) 228 } 229 }; 230 231 /* 232 * I2C3: 233 * 0x11 ... ES8283 234 * 0x50 ... LCD EDID 235 * 0x56 ... EEPROM 236 */ 237 static struct i2c_pads_info i2c_pad_info2 = { 238 .scl = { 239 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, 240 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, 241 .gp = IMX_GPIO_NR(3, 17) 242 }, 243 .sda = { 244 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, 245 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, 246 .gp = IMX_GPIO_NR(3, 18) 247 } 248 }; 249 250 static void novena_spl_setup_iomux_i2c(void) 251 { 252 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); 253 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 254 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); 255 } 256 257 /* 258 * PCI express 259 */ 260 #ifdef CONFIG_CMD_PCI 261 static iomux_v3_cfg_t pcie_pads[] = { 262 /* "Reset" pin */ 263 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 264 /* "Power on" pin */ 265 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), 266 /* "Wake up" pin (input) */ 267 MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), 268 /* "Disable endpoint" (rfkill) pin */ 269 MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), 270 }; 271 272 static void novena_spl_setup_iomux_pcie(void) 273 { 274 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); 275 276 /* Ensure PCIe is powered down */ 277 gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0); 278 279 /* Put the card into reset */ 280 gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0); 281 282 /* Input signal to wake system from mPCIe card */ 283 gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO); 284 285 /* Drive RFKILL high, to ensure the radio is turned on */ 286 gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1); 287 } 288 #else 289 static inline void novena_spl_setup_iomux_pcie(void) {} 290 #endif 291 292 /* 293 * SDHC 294 */ 295 static iomux_v3_cfg_t usdhc2_pads[] = { 296 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 297 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 298 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 299 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 300 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 301 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 302 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ 303 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ 304 }; 305 306 static iomux_v3_cfg_t usdhc3_pads[] = { 307 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 308 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 309 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 310 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 311 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 312 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 313 }; 314 315 static void novena_spl_setup_iomux_sdhc(void) 316 { 317 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 318 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 319 320 /* Big SD write-protect and card-detect */ 321 gpio_direction_input(IMX_GPIO_NR(1, 2)); 322 gpio_direction_input(IMX_GPIO_NR(1, 4)); 323 } 324 325 /* 326 * SPI 327 */ 328 #ifdef CONFIG_MXC_SPI 329 static iomux_v3_cfg_t ecspi3_pads[] = { 330 /* SS1 */ 331 MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), 332 MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), 333 MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), 334 MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL), 335 MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL), 336 MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL), 337 MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL), 338 }; 339 340 static void novena_spl_setup_iomux_spi(void) 341 { 342 imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); 343 /* De-assert the nCS */ 344 gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1); 345 gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1); 346 gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1); 347 } 348 #else 349 static void novena_spl_setup_iomux_spi(void) {} 350 #endif 351 352 /* 353 * UART 354 */ 355 static iomux_v3_cfg_t const uart2_pads[] = { 356 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 357 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 358 }; 359 360 static iomux_v3_cfg_t const uart3_pads[] = { 361 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 362 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 363 }; 364 365 static iomux_v3_cfg_t const uart4_pads[] = { 366 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 367 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 368 MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 369 MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), 370 371 }; 372 373 static void novena_spl_setup_iomux_uart(void) 374 { 375 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); 376 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); 377 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); 378 } 379 380 /* 381 * Video 382 */ 383 #ifdef CONFIG_VIDEO 384 static iomux_v3_cfg_t hdmi_pads[] = { 385 /* "Ghost HPD" pin */ 386 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), 387 388 /* LCD_PWR_CTL */ 389 MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), 390 /* LCD_BL_ON */ 391 MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), 392 /* GPIO_PWM1 */ 393 MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 394 }; 395 396 static void novena_spl_setup_iomux_video(void) 397 { 398 imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads)); 399 gpio_direction_input(NOVENA_HDMI_GHOST_HPD); 400 } 401 #else 402 static inline void novena_spl_setup_iomux_video(void) {} 403 #endif 404 405 /* 406 * SPL boots from uSDHC card 407 */ 408 #ifdef CONFIG_FSL_ESDHC 409 static struct fsl_esdhc_cfg usdhc_cfg = { 410 USDHC3_BASE_ADDR, 0, 4 411 }; 412 413 int board_mmc_getcd(struct mmc *mmc) 414 { 415 /* There is no CD for a microSD card, assume always present. */ 416 return 1; 417 } 418 419 int board_mmc_init(bd_t *bis) 420 { 421 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 422 return fsl_esdhc_initialize(bis, &usdhc_cfg); 423 } 424 #endif 425 426 /* Configure MX6Q/DUAL mmdc DDR io registers */ 427 static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = { 428 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ 429 .dram_sdclk_0 = 0x00020038, 430 .dram_sdclk_1 = 0x00020038, 431 .dram_cas = 0x00000038, 432 .dram_ras = 0x00000038, 433 .dram_reset = 0x00000038, 434 /* SDCKE[0:1]: 100k pull-up */ 435 .dram_sdcke0 = 0x00000038, 436 .dram_sdcke1 = 0x00000038, 437 /* SDBA2: pull-up disabled */ 438 .dram_sdba2 = 0x00000000, 439 /* SDODT[0:1]: 100k pull-up, 40 ohm */ 440 .dram_sdodt0 = 0x00000038, 441 .dram_sdodt1 = 0x00000038, 442 /* SDQS[0:7]: Differential input, 40 ohm */ 443 .dram_sdqs0 = 0x00000038, 444 .dram_sdqs1 = 0x00000038, 445 .dram_sdqs2 = 0x00000038, 446 .dram_sdqs3 = 0x00000038, 447 .dram_sdqs4 = 0x00000038, 448 .dram_sdqs5 = 0x00000038, 449 .dram_sdqs6 = 0x00000038, 450 .dram_sdqs7 = 0x00000038, 451 452 /* DQM[0:7]: Differential input, 40 ohm */ 453 .dram_dqm0 = 0x00000038, 454 .dram_dqm1 = 0x00000038, 455 .dram_dqm2 = 0x00000038, 456 .dram_dqm3 = 0x00000038, 457 .dram_dqm4 = 0x00000038, 458 .dram_dqm5 = 0x00000038, 459 .dram_dqm6 = 0x00000038, 460 .dram_dqm7 = 0x00000038, 461 }; 462 463 /* Configure MX6Q/DUAL mmdc GRP io registers */ 464 static struct mx6dq_iomux_grp_regs novena_grp_ioregs = { 465 /* DDR3 */ 466 .grp_ddr_type = 0x000c0000, 467 .grp_ddrmode_ctl = 0x00020000, 468 /* Disable DDR pullups */ 469 .grp_ddrpke = 0x00000000, 470 /* ADDR[00:16], SDBA[0:1]: 40 ohm */ 471 .grp_addds = 0x00000038, 472 /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ 473 .grp_ctlds = 0x00000038, 474 /* DATA[00:63]: Differential input, 40 ohm */ 475 .grp_ddrmode = 0x00020000, 476 .grp_b0ds = 0x00000038, 477 .grp_b1ds = 0x00000038, 478 .grp_b2ds = 0x00000038, 479 .grp_b3ds = 0x00000038, 480 .grp_b4ds = 0x00000038, 481 .grp_b5ds = 0x00000038, 482 .grp_b6ds = 0x00000038, 483 .grp_b7ds = 0x00000038, 484 }; 485 486 static struct mx6_mmdc_calibration novena_mmdc_calib = { 487 /* write leveling calibration determine */ 488 .p0_mpwldectrl0 = 0x00420048, 489 .p0_mpwldectrl1 = 0x006f0059, 490 .p1_mpwldectrl0 = 0x005a0104, 491 .p1_mpwldectrl1 = 0x01070113, 492 /* Read DQS Gating calibration */ 493 .p0_mpdgctrl0 = 0x437c040b, 494 .p0_mpdgctrl1 = 0x0413040e, 495 .p1_mpdgctrl0 = 0x444f0446, 496 .p1_mpdgctrl1 = 0x044d0422, 497 /* Read Calibration: DQS delay relative to DQ read access */ 498 .p0_mprddlctl = 0x4c424249, 499 .p1_mprddlctl = 0x4e48414f, 500 /* Write Calibration: DQ/DM delay relative to DQS write access */ 501 .p0_mpwrdlctl = 0x42414641, 502 .p1_mpwrdlctl = 0x46374b43, 503 }; 504 505 static struct mx6_ddr_sysinfo novena_ddr_info = { 506 /* Width of data bus: 0=16, 1=32, 2=64 */ 507 .dsize = 2, 508 /* Config for full 4GB range so that get_mem_size() works */ 509 .cs_density = 32, /* 32Gb per CS */ 510 /* Single chip select */ 511 .ncs = 1, 512 .cs1_mirror = 0, 513 .rtt_wr = 0, /* RTT_Wr = RZQ/4 */ 514 .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ 515 .walat = 0, /* Write additional latency */ 516 .ralat = 5, /* Read additional latency */ 517 .mif3_mode = 3, /* Command prediction working mode */ 518 .bi_on = 1, /* Bank interleaving enabled */ 519 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 520 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 521 .refsel = 1, /* Refresh cycles at 32KHz */ 522 .refr = 7, /* 8 refresh commands per refresh cycle */ 523 }; 524 525 static struct mx6_ddr3_cfg elpida_4gib_1600 = { 526 .mem_speed = 1600, 527 .density = 4, 528 .width = 64, 529 .banks = 8, 530 .rowaddr = 16, 531 .coladdr = 10, 532 .pagesz = 2, 533 .trcd = 1375, 534 .trcmin = 4875, 535 .trasmin = 3500, 536 }; 537 538 static void ccgr_init(void) 539 { 540 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 541 542 writel(0x00C03F3F, &ccm->CCGR0); 543 writel(0x0030FC03, &ccm->CCGR1); 544 writel(0x0FFFC000, &ccm->CCGR2); 545 writel(0x3FF00000, &ccm->CCGR3); 546 writel(0xFFFFF300, &ccm->CCGR4); 547 writel(0x0F0000C3, &ccm->CCGR5); 548 writel(0x000003FF, &ccm->CCGR6); 549 } 550 551 /* 552 * called from C runtime startup code (arch/arm/lib/crt0.S:_main) 553 * - we have a stack and a place to store GD, both in SRAM 554 * - no variable global data is available 555 */ 556 void board_init_f(ulong dummy) 557 { 558 /* setup AIPS and disable watchdog */ 559 arch_cpu_init(); 560 561 ccgr_init(); 562 gpr_init(); 563 564 /* setup GP timer */ 565 timer_init(); 566 567 #ifdef CONFIG_BOARD_POSTCLK_INIT 568 board_postclk_init(); 569 #endif 570 #ifdef CONFIG_FSL_ESDHC 571 get_clocks(); 572 #endif 573 574 /* Setup IOMUX and configure basics. */ 575 novena_spl_setup_iomux_audio(); 576 novena_spl_setup_iomux_buttons(); 577 novena_spl_setup_iomux_enet(); 578 novena_spl_setup_iomux_fpga(); 579 novena_spl_setup_iomux_i2c(); 580 novena_spl_setup_iomux_pcie(); 581 novena_spl_setup_iomux_sdhc(); 582 novena_spl_setup_iomux_spi(); 583 novena_spl_setup_iomux_uart(); 584 novena_spl_setup_iomux_video(); 585 586 /* UART clocks enabled and gd valid - init serial console */ 587 preloader_console_init(); 588 589 /* Start the DDR DRAM */ 590 mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs); 591 mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600); 592 593 /* Perform DDR DRAM calibration */ 594 udelay(100); 595 mmdc_do_write_level_calibration(&novena_ddr_info); 596 mmdc_do_dqs_calibration(&novena_ddr_info); 597 } 598