1 /* 2 * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 3 * (C) Copyright 2012 Renesas Solutions Corp. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 #include <asm/io.h> 26 #include <asm/arch/sys_proto.h> 27 #include <asm/gpio.h> 28 #include <netdev.h> 29 #include <i2c.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define CS0BCR_D (0x06C00400) 34 #define CS4BCR_D (0x06C00400) 35 #define CS0WCR_D (0x55062C42) 36 #define CS4WCR_D (0x19051443) 37 #define CMNCR_BROMMD0 (1 << 21) 38 #define CMNCR_BROMMD1 (1 << 22) 39 #define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) 40 #define VCLKCR1_D (0x27) 41 42 #define SMSTPCR1_CMT0 (1 << 24) 43 #define SMSTPCR1_I2C0 (1 << 16) 44 #define SMSTPCR3_USB (1 << 22) 45 46 #define PORT32CR (0xE6051020) 47 #define PORT33CR (0xE6051021) 48 #define PORT34CR (0xE6051022) 49 #define PORT35CR (0xE6051023) 50 51 static int cmp_loop(u32 *addr, u32 data, u32 cmp) 52 { 53 int err = -1; 54 int timeout = 100; 55 u32 value; 56 57 while (timeout > 0) { 58 value = readl(addr); 59 if ((value & data) == cmp) { 60 err = 0; 61 break; 62 } 63 timeout--; 64 } 65 66 return err; 67 } 68 69 /* SBSC Init function */ 70 static void sbsc_init(struct sh73a0_sbsc *sbsc) 71 { 72 writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); 73 writel(0x5, &sbsc->sdgencnt); 74 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 75 76 writel(0xacc90159, &sbsc->sdcr0); 77 writel(0x00010059, &sbsc->sdcr1); 78 writel(0x50874114, &sbsc->sdwcrc0); 79 writel(0x33199b37, &sbsc->sdwcrc1); 80 writel(0x008f2313, &sbsc->sdwcrc2); 81 writel(0x31020707, &sbsc->sdwcr00); 82 writel(0x0017040a, &sbsc->sdwcr01); 83 writel(0x31020707, &sbsc->sdwcr10); 84 writel(0x0017040a, &sbsc->sdwcr11); 85 writel(0x05555555, &sbsc->sddrvcr0); 86 writel(0x30000000, &sbsc->sdwcr2); 87 88 writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); 89 cmp_loop(&sbsc->sdpcr, 0x80, 0x80); 90 91 writel(0x00002710, &sbsc->sdgencnt); 92 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 93 94 writel(0x0000003f, &sbsc->sdmracr0); 95 writel(0x0, SDMRA1A); 96 writel(0x000001f4, &sbsc->sdgencnt); 97 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 98 99 writel(0x0000ff0a, &sbsc->sdmracr0); 100 if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) 101 writel(0x0, SDMRA3A); 102 else 103 writel(0x0, SDMRA3B); 104 105 writel(0x00000032, &sbsc->sdgencnt); 106 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); 107 108 if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { 109 writel(0x00002201, &sbsc->sdmracr0); 110 writel(0x0, SDMRA1A); 111 writel(0x00000402, &sbsc->sdmracr0); 112 writel(0x0, SDMRA1A); 113 writel(0x00000403, &sbsc->sdmracr0); 114 writel(0x0, SDMRA1A); 115 writel(0x0, SDMRA2A); 116 } else { 117 writel(0x00002201, &sbsc->sdmracr0); 118 writel(0x0, SDMRA1B); 119 writel(0x00000402, &sbsc->sdmracr0); 120 writel(0x0, SDMRA1B); 121 writel(0x00000403, &sbsc->sdmracr0); 122 writel(0x0, SDMRA1B); 123 writel(0x0, SDMRA2B); 124 } 125 126 writel(0x88800004, &sbsc->sdmrtmpcr); 127 writel(0x00000004, &sbsc->sdmrtmpmsk); 128 writel(0xa55a0032, &sbsc->rtcor); 129 writel(0xa55a000c, &sbsc->rtcorh); 130 writel(0xa55a2048, &sbsc->rtcsr); 131 writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); 132 writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); 133 writel(0xfff20000, &sbsc->zqccr); 134 135 /* SCBS2 only */ 136 if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { 137 writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); 138 writel(0xa5390000, &sbsc->dphycnt1); 139 writel(0x00001200, &sbsc->dphycnt0); 140 writel(0x07ce0000, &sbsc->dphycnt1); 141 writel(0x00001247, &sbsc->dphycnt0); 142 cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); 143 writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); 144 } 145 } 146 147 void s_init(void) 148 { 149 struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; 150 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; 151 struct sh73a0_sbsc_cpg_srcr *cpg_srcr = 152 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; 153 struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; 154 struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; 155 struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; 156 struct sh73a0_hpb_bscr *hpb_bscr = 157 (struct sh73a0_hpb_bscr *)HPBSCR_BASE; 158 159 /* Watchdog init */ 160 writew(0xA507, &rwdt->rwtcsra0); 161 162 /* Secure control register Init */ 163 #define LIFEC_SEC_SRC_BIT (1 << 15) 164 writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); 165 166 clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); 167 clrbits_le32(&cpg->smstpcr2, (1 << 18)); 168 clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); 169 writel(0x0, &cpg->pllecr); 170 171 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); 172 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 173 174 writel(0x2D000000, &cpg->pll0cr); 175 writel(0x17100000, &cpg->pll1cr); 176 writel(0x96235880, &cpg->frqcrb); 177 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 178 179 writel(0xB, &cpg->flckcr); 180 clrbits_le32(&cpg->smstpcr0, (1 << 1)); 181 182 clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); 183 writel(0x0514, &hpb_bscr->smgpiotime); 184 writel(0x0514, &hpb_bscr->smcmt2time); 185 writel(0x0514, &hpb_bscr->smcpgtime); 186 writel(0x0514, &hpb_bscr->smsysctime); 187 188 writel(0x00092000, &cpg->dvfscr4); 189 writel(0x000000DC, &cpg->dvfscr5); 190 writel(0x0, &cpg->pllecr); 191 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); 192 193 /* FRQCR Init */ 194 writel(0x0012453C, &cpg->frqcra); 195 writel(0x80331350, &cpg->frqcrb); 196 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); 197 writel(0x00000B0B, &cpg->frqcrd); 198 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 199 200 /* Clock Init */ 201 writel(0x00000003, PCLKCR); 202 writel(0x0000012F, &cpg->vclkcr1); 203 writel(0x00000119, &cpg->vclkcr2); 204 writel(0x00000119, &cpg->vclkcr3); 205 writel(0x00000002, &cpg->zbckcr); 206 writel(0x00000005, &cpg->flckcr); 207 writel(0x00000080, &cpg->sd0ckcr); 208 writel(0x00000080, &cpg->sd1ckcr); 209 writel(0x00000080, &cpg->sd2ckcr); 210 writel(0x0000003F, &cpg->fsiackcr); 211 writel(0x0000003F, &cpg->fsibckcr); 212 writel(0x00000080, &cpg->subckcr); 213 writel(0x0000000B, &cpg->spuackcr); 214 writel(0x0000000B, &cpg->spuvckcr); 215 writel(0x0000013F, &cpg->msuckcr); 216 writel(0x00000080, &cpg->hsickcr); 217 writel(0x0000003F, &cpg->mfck1cr); 218 writel(0x0000003F, &cpg->mfck2cr); 219 writel(0x00000107, &cpg->dsitckcr); 220 writel(0x00000313, &cpg->dsi0pckcr); 221 writel(0x0000130D, &cpg->dsi1pckcr); 222 writel(0x2A800E0E, &cpg->dsi0phycr); 223 writel(0x1E000000, &cpg->pll0cr); 224 writel(0x2D000000, &cpg->pll0cr); 225 writel(0x17100000, &cpg->pll1cr); 226 writel(0x27000080, &cpg->pll2cr); 227 writel(0x1D000000, &cpg->pll3cr); 228 writel(0x00080000, &cpg->pll0stpcr); 229 writel(0x000120C0, &cpg->pll1stpcr); 230 writel(0x00012000, &cpg->pll2stpcr); 231 writel(0x00000030, &cpg->pll3stpcr); 232 233 writel(0x0000000B, &cpg->pllecr); 234 cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); 235 236 writel(0x000120F0, &cpg->dvfscr3); 237 writel(0x00000020, &cpg->mpmode); 238 writel(0x0000028A, &cpg->vrefcr); 239 writel(0xE4628087, &cpg->rmstpcr0); 240 writel(0xFFFFFFFF, &cpg->rmstpcr1); 241 writel(0x53FFFFFF, &cpg->rmstpcr2); 242 writel(0xFFFFFFFF, &cpg->rmstpcr3); 243 writel(0x00800D3D, &cpg->rmstpcr4); 244 writel(0xFFFFF3FF, &cpg->rmstpcr5); 245 writel(0x00000000, &cpg->smstpcr2); 246 writel(0x00040000, &cpg_srcr->srcr2); 247 248 clrbits_le32(&cpg->pllecr, (1 << 3)); 249 cmp_loop(&cpg->pllecr, 0x00000800, 0x0); 250 251 writel(0x00000001, &hpb->hpbctrl6); 252 cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); 253 254 writel(0x00001414, &cpg->frqcrd); 255 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 256 257 writel(0x1d000000, &cpg->pll3cr); 258 setbits_le32(&cpg->pllecr, (1 << 3)); 259 cmp_loop(&cpg->pllecr, 0x800, 0x800); 260 261 /* SBSC1 Init*/ 262 sbsc_init(sbsc1); 263 264 /* SBSC2 Init*/ 265 sbsc_init(sbsc2); 266 267 writel(0x00000b0b, &cpg->frqcrd); 268 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); 269 } 270 271 int board_early_init_f(void) 272 { 273 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; 274 struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; 275 struct sh73a0_sbsc_cpg_srcr *cpg_srcr = 276 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; 277 278 writel(CS0BCR_D, &bsc->cs0bcr); 279 writel(CS4BCR_D, &bsc->cs4bcr); 280 writel(CS0WCR_D, &bsc->cs0wcr); 281 writel(CS4WCR_D, &bsc->cs4wcr); 282 283 clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); 284 285 clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); 286 clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); 287 clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB); 288 clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB); 289 writel(VCLKCR1_D, &cpg->vclkcr1); 290 291 /* Setup SCIF4 / workaround */ 292 writeb(0x12, PORT32CR); 293 writeb(0x22, PORT33CR); 294 writeb(0x12, PORT34CR); 295 writeb(0x22, PORT35CR); 296 297 return 0; 298 } 299 300 int board_init(void) 301 { 302 sh73a0_pinmux_init(); 303 304 /* SCIFA 4 */ 305 gpio_request(GPIO_FN_SCIFA4_TXD, NULL); 306 gpio_request(GPIO_FN_SCIFA4_RXD, NULL); 307 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); 308 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); 309 310 /* Ethernet/SMSC */ 311 gpio_request(GPIO_PORT224, NULL); 312 gpio_direction_input(GPIO_PORT224); 313 314 /* SMSC/USB */ 315 gpio_request(GPIO_FN_CS4_, NULL); 316 317 /* MMCIF */ 318 gpio_request(GPIO_FN_MMCCLK0, NULL); 319 gpio_request(GPIO_FN_MMCCMD0_PU, NULL); 320 gpio_request(GPIO_FN_MMCD0_0_PU, NULL); 321 gpio_request(GPIO_FN_MMCD0_1_PU, NULL); 322 gpio_request(GPIO_FN_MMCD0_2_PU, NULL); 323 gpio_request(GPIO_FN_MMCD0_3_PU, NULL); 324 gpio_request(GPIO_FN_MMCD0_4_PU, NULL); 325 gpio_request(GPIO_FN_MMCD0_5_PU, NULL); 326 gpio_request(GPIO_FN_MMCD0_6_PU, NULL); 327 gpio_request(GPIO_FN_MMCD0_7_PU, NULL); 328 329 /* SDHI */ 330 gpio_request(GPIO_FN_SDHIWP0, NULL); 331 gpio_request(GPIO_FN_SDHICD0, NULL); 332 gpio_request(GPIO_FN_SDHICMD0, NULL); 333 gpio_request(GPIO_FN_SDHICLK0, NULL); 334 gpio_request(GPIO_FN_SDHID0_3, NULL); 335 gpio_request(GPIO_FN_SDHID0_2, NULL); 336 gpio_request(GPIO_FN_SDHID0_1, NULL); 337 gpio_request(GPIO_FN_SDHID0_0, NULL); 338 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); 339 gpio_request(GPIO_PORT15, NULL); 340 gpio_direction_output(GPIO_PORT15, 1); 341 342 /* I2C */ 343 gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); 344 gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); 345 346 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); 347 348 return 0; 349 } 350 351 const struct rmobile_sysinfo sysinfo = { 352 CONFIG_RMOBILE_BOARD_STRING 353 }; 354 355 int dram_init(void) 356 { 357 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 358 return 0; 359 } 360 361 int board_eth_init(bd_t *bis) 362 { 363 int ret = 0; 364 #ifdef CONFIG_SMC911X 365 ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); 366 #endif 367 return ret; 368 } 369 370 void reset_cpu(ulong addr) 371 { 372 } 373