1 /* 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. 3 * Dave Liu <daveliu@freescale.com> 4 * 5 * Copyright (C) 2007 Logic Product Development, Inc. 6 * Peter Barada <peterb@logicpd.com> 7 * 8 * Copyright (C) 2007 MontaVista Software, Inc. 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 * 11 * (C) Copyright 2008 - 2010 12 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <common.h> 18 #include <ioports.h> 19 #include <mpc83xx.h> 20 #include <i2c.h> 21 #include <miiphy.h> 22 #include <asm/io.h> 23 #include <asm/mmu.h> 24 #include <asm/processor.h> 25 #include <pci.h> 26 #include <libfdt.h> 27 #include <post.h> 28 29 #include "../common/common.h" 30 31 const qe_iop_conf_t qe_iop_conf_tab[] = { 32 /* port pin dir open_drain assign */ 33 #if defined(CONFIG_MPC8360) 34 /* MDIO */ 35 {0, 1, 3, 0, 2}, /* MDIO */ 36 {0, 2, 1, 0, 1}, /* MDC */ 37 38 /* UCC4 - UEC */ 39 {1, 14, 1, 0, 1}, /* TxD0 */ 40 {1, 15, 1, 0, 1}, /* TxD1 */ 41 {1, 20, 2, 0, 1}, /* RxD0 */ 42 {1, 21, 2, 0, 1}, /* RxD1 */ 43 {1, 18, 1, 0, 1}, /* TX_EN */ 44 {1, 26, 2, 0, 1}, /* RX_DV */ 45 {1, 27, 2, 0, 1}, /* RX_ER */ 46 {1, 24, 2, 0, 1}, /* COL */ 47 {1, 25, 2, 0, 1}, /* CRS */ 48 {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ 49 {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ 50 51 /* DUART - UART2 */ 52 {5, 0, 1, 0, 2}, /* UART2_SOUT */ 53 {5, 2, 1, 0, 1}, /* UART2_RTS */ 54 {5, 3, 2, 0, 2}, /* UART2_SIN */ 55 {5, 1, 2, 0, 3}, /* UART2_CTS */ 56 #elif !defined(CONFIG_MPC8309) 57 /* Local Bus */ 58 {0, 16, 1, 0, 3}, /* LA00 */ 59 {0, 17, 1, 0, 3}, /* LA01 */ 60 {0, 18, 1, 0, 3}, /* LA02 */ 61 {0, 19, 1, 0, 3}, /* LA03 */ 62 {0, 20, 1, 0, 3}, /* LA04 */ 63 {0, 21, 1, 0, 3}, /* LA05 */ 64 {0, 22, 1, 0, 3}, /* LA06 */ 65 {0, 23, 1, 0, 3}, /* LA07 */ 66 {0, 24, 1, 0, 3}, /* LA08 */ 67 {0, 25, 1, 0, 3}, /* LA09 */ 68 {0, 26, 1, 0, 3}, /* LA10 */ 69 {0, 27, 1, 0, 3}, /* LA11 */ 70 {0, 28, 1, 0, 3}, /* LA12 */ 71 {0, 29, 1, 0, 3}, /* LA13 */ 72 {0, 30, 1, 0, 3}, /* LA14 */ 73 {0, 31, 1, 0, 3}, /* LA15 */ 74 75 /* MDIO */ 76 {3, 4, 3, 0, 2}, /* MDIO */ 77 {3, 5, 1, 0, 2}, /* MDC */ 78 79 /* UCC4 - UEC */ 80 {1, 18, 1, 0, 1}, /* TxD0 */ 81 {1, 19, 1, 0, 1}, /* TxD1 */ 82 {1, 22, 2, 0, 1}, /* RxD0 */ 83 {1, 23, 2, 0, 1}, /* RxD1 */ 84 {1, 26, 2, 0, 1}, /* RxER */ 85 {1, 28, 2, 0, 1}, /* Rx_DV */ 86 {1, 30, 1, 0, 1}, /* TxEN */ 87 {1, 31, 2, 0, 1}, /* CRS */ 88 {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ 89 #endif 90 91 /* END of table */ 92 {0, 0, 0, 0, QE_IOP_TAB_END}, 93 }; 94 95 static int board_init_i2c_busses(void) 96 { 97 I2C_MUX_DEVICE *dev = NULL; 98 uchar *dtt_bus = (uchar *)"pca9547:70:a"; 99 100 /* Set up the Bus for the DTTs */ 101 dev = i2c_mux_ident_muxstring(dtt_bus); 102 if (dev == NULL) 103 printf("Error couldn't add Bus for DTT\n"); 104 105 return 0; 106 } 107 108 #if defined(CONFIG_SUVD3) 109 const uint upma_table[] = { 110 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */ 111 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */ 112 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */ 113 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */ 114 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */ 115 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */ 116 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */ 117 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */ 118 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */ 119 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */ 120 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */ 121 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */ 122 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */ 123 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */ 124 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */ 125 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */ 126 }; 127 #endif 128 129 static int piggy_present(void) 130 { 131 struct km_bec_fpga __iomem *base = 132 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; 133 134 return in_8(&base->bprth) & PIGGY_PRESENT; 135 } 136 137 #if defined(CONFIG_KMVECT1) 138 int ethernet_present(void) 139 { 140 /* ethernet port connected to simple switch without piggy */ 141 return 1; 142 } 143 #else 144 int ethernet_present(void) 145 { 146 return piggy_present(); 147 } 148 #endif 149 150 151 int board_early_init_r(void) 152 { 153 struct km_bec_fpga *base = 154 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 155 #if defined(CONFIG_SUVD3) 156 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; 157 fsl_lbc_t *lbc = &immap->im_lbc; 158 u32 *mxmr = &lbc->mamr; 159 #endif 160 161 #if defined(CONFIG_MPC8360) 162 unsigned short svid; 163 /* 164 * Because of errata in the UCCs, we have to write to the reserved 165 * registers to slow the clocks down. 166 */ 167 svid = SVR_REV(mfspr(SVR)); 168 switch (svid) { 169 case 0x0020: 170 /* 171 * MPC8360ECE.pdf QE_ENET10 table 4: 172 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2) 173 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1) 174 */ 175 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000); 176 break; 177 case 0x0021: 178 /* 179 * MPC8360ECE.pdf QE_ENET10 table 4: 180 * IMMR + 0x14AC[24:27] = 1010 181 */ 182 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac), 183 0x00000050, 0x000000a0); 184 break; 185 } 186 #endif 187 188 /* enable the PHY on the PIGGY */ 189 setbits_8(&base->pgy_eth, 0x01); 190 /* enable the Unit LED (green) */ 191 setbits_8(&base->oprth, WRL_BOOT); 192 /* enable Application Buffer */ 193 setbits_8(&base->oprtl, OPRTL_XBUFENA); 194 195 #if defined(CONFIG_SUVD3) 196 /* configure UPMA for APP1 */ 197 upmconfig(UPMA, (uint *) upma_table, 198 sizeof(upma_table) / sizeof(uint)); 199 out_be32(mxmr, CONFIG_SYS_MAMR); 200 #endif 201 return 0; 202 } 203 204 int misc_init_r(void) 205 { 206 /* add board specific i2c busses */ 207 board_init_i2c_busses(); 208 return 0; 209 } 210 211 #if defined(CONFIG_KMVECT1) 212 #include <mv88e6352.h> 213 /* Marvell MV88E6122 switch configuration */ 214 static struct mv88e_sw_reg extsw_conf[] = { 215 /* port 1, FRONT_MDI, autoneg */ 216 { PORT(1), PORT_PHY, NO_SPEED_FOR }, 217 { PORT(1), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 218 { PHY(1), PHY_1000_CTRL, NO_ADV }, 219 { PHY(1), PHY_SPEC_CTRL, AUTO_MDIX_EN }, 220 { PHY(1), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | 221 FULL_DUPLEX }, 222 /* port 2, unused */ 223 { PORT(2), PORT_CTRL, PORT_DIS }, 224 { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, 225 { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, 226 /* port 3, BP_MII (CPU), PHY mode, 100BASE */ 227 { PORT(3), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 228 /* port 4, ESTAR to slot 11, SerDes, 1000BASE-X */ 229 { PORT(4), PORT_STATUS, NO_PHY_DETECT }, 230 { PORT(4), PORT_PHY, SPEED_1000_FOR }, 231 { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 232 /* port 5, ESTAR to slot 13, SerDes, 1000BASE-X */ 233 { PORT(5), PORT_STATUS, NO_PHY_DETECT }, 234 { PORT(5), PORT_PHY, SPEED_1000_FOR }, 235 { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, 236 /* 237 * Errata Fix: 1.9V Output from Internal 1.8V Regulator, 238 * acc . MV-S300889-00D.pdf , clause 4.5 239 */ 240 { PORT(5), 0x1A, 0xADB1 }, 241 /* port 6, unused, this port has no phy */ 242 { PORT(6), PORT_CTRL, PORT_DIS }, 243 }; 244 #endif 245 246 int last_stage_init(void) 247 { 248 #if defined(CONFIG_KMVECT1) 249 struct km_bec_fpga __iomem *base = 250 (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE; 251 u8 tmp_reg; 252 253 /* Release mv88e6122 from reset */ 254 tmp_reg = in_8(&base->res1[0]) | 0x10; /* DIRECT3 register */ 255 out_8(&base->res1[0], tmp_reg); /* GP28 as output */ 256 tmp_reg = in_8(&base->gprt3) | 0x10; /* GP28 to high */ 257 out_8(&base->gprt3, tmp_reg); 258 259 /* configure MV88E6122 switch */ 260 char *name = "UEC2"; 261 262 if (miiphy_set_current_dev(name)) 263 return 0; 264 265 mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, 266 ARRAY_SIZE(extsw_conf)); 267 268 mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); 269 270 if (piggy_present()) { 271 setenv("ethact", "UEC2"); 272 setenv("netdev", "eth1"); 273 puts("using PIGGY for network boot\n"); 274 } else { 275 setenv("netdev", "eth0"); 276 puts("using frontport for network boot\n"); 277 } 278 #endif 279 280 #if defined(CONFIG_KMCOGE5NE) 281 struct bfticu_iomap *base = 282 (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE; 283 u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK; 284 285 if (dip_switch != 0) { 286 /* start bootloader */ 287 puts("DIP: Enabled\n"); 288 setenv("actual_bank", "0"); 289 } 290 #endif 291 set_km_env(); 292 return 0; 293 } 294 295 int fixed_sdram(void) 296 { 297 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 298 u32 msize = 0; 299 u32 ddr_size; 300 u32 ddr_size_log2; 301 302 out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e)); 303 out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f); 304 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); 305 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); 306 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); 307 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); 308 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); 309 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); 310 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); 311 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); 312 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); 313 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); 314 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL); 315 udelay(200); 316 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); 317 318 msize = CONFIG_SYS_DDR_SIZE << 20; 319 disable_addr_trans(); 320 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize); 321 enable_addr_trans(); 322 msize /= (1024 * 1024); 323 if (CONFIG_SYS_DDR_SIZE != msize) { 324 for (ddr_size = msize << 20, ddr_size_log2 = 0; 325 (ddr_size > 1); 326 ddr_size = ddr_size >> 1, ddr_size_log2++) 327 if (ddr_size & 1) 328 return -1; 329 out_be32(&im->sysconf.ddrlaw[0].ar, 330 (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE))); 331 out_be32(&im->ddr.csbnds[0].csbnds, 332 (((msize / 16) - 1) & 0xff)); 333 } 334 335 return msize; 336 } 337 338 phys_size_t initdram(int board_type) 339 { 340 immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 341 u32 msize = 0; 342 343 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) 344 return -1; 345 346 out_be32(&im->sysconf.ddrlaw[0].bar, 347 CONFIG_SYS_DDR_BASE & LAWBAR_BAR); 348 msize = fixed_sdram(); 349 350 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) 351 /* 352 * Initialize DDR ECC byte 353 */ 354 ddr_enable_ecc(msize * 1024 * 1024); 355 #endif 356 357 /* return total bus SDRAM size(bytes) -- DDR */ 358 return msize * 1024 * 1024; 359 } 360 361 int checkboard(void) 362 { 363 puts("Board: Keymile " CONFIG_KM_BOARD_NAME); 364 365 if (piggy_present()) 366 puts(" with PIGGY."); 367 puts("\n"); 368 return 0; 369 } 370 371 #if defined(CONFIG_OF_BOARD_SETUP) 372 void ft_board_setup(void *blob, bd_t *bd) 373 { 374 ft_cpu_setup(blob, bd); 375 } 376 #endif 377 378 #if defined(CONFIG_HUSH_INIT_VAR) 379 int hush_init_var(void) 380 { 381 ivm_read_eeprom(); 382 return 0; 383 } 384 #endif 385 386 #if defined(CONFIG_POST) 387 int post_hotkeys_pressed(void) 388 { 389 int testpin = 0; 390 struct km_bec_fpga *base = 391 (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE; 392 int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG); 393 testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0; 394 debug("post_hotkeys_pressed: %d\n", !testpin); 395 return testpin; 396 } 397 398 ulong post_word_load(void) 399 { 400 void* addr = (ulong *) (CPM_POST_WORD_ADDR); 401 debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr)); 402 return in_le32(addr); 403 404 } 405 void post_word_store(ulong value) 406 { 407 void* addr = (ulong *) (CPM_POST_WORD_ADDR); 408 debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value); 409 out_le32(addr, value); 410 } 411 412 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) 413 { 414 *vstart = CONFIG_SYS_MEMTEST_START; 415 *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START; 416 debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size); 417 418 return 0; 419 } 420 #endif 421