1 /* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * Copyright (C) 2013 Imagination Technologies 4 * 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #include <common.h> 9 #include <netdev.h> 10 #include <pci_gt64120.h> 11 #include <pci_msc01.h> 12 #include <serial.h> 13 14 #include <asm/addrspace.h> 15 #include <asm/io.h> 16 #include <asm/malta.h> 17 18 #include "superio.h" 19 20 enum core_card { 21 CORE_UNKNOWN, 22 CORE_LV, 23 CORE_FPGA6, 24 }; 25 26 enum sys_con { 27 SYSCON_UNKNOWN, 28 SYSCON_GT64120, 29 SYSCON_MSC01, 30 }; 31 32 static enum core_card malta_core_card(void) 33 { 34 u32 corid, rev; 35 36 rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); 37 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; 38 39 switch (corid) { 40 case MALTA_REVISION_CORID_CORE_LV: 41 return CORE_LV; 42 43 case MALTA_REVISION_CORID_CORE_FPGA6: 44 return CORE_FPGA6; 45 46 default: 47 return CORE_UNKNOWN; 48 } 49 } 50 51 static enum sys_con malta_sys_con(void) 52 { 53 switch (malta_core_card()) { 54 case CORE_LV: 55 return SYSCON_GT64120; 56 57 case CORE_FPGA6: 58 return SYSCON_MSC01; 59 60 default: 61 return SYSCON_UNKNOWN; 62 } 63 } 64 65 phys_size_t initdram(int board_type) 66 { 67 return CONFIG_SYS_MEM_SIZE; 68 } 69 70 int checkboard(void) 71 { 72 enum core_card core; 73 74 puts("Board: MIPS Malta"); 75 76 core = malta_core_card(); 77 switch (core) { 78 case CORE_LV: 79 puts(" CoreLV"); 80 break; 81 82 case CORE_FPGA6: 83 puts(" CoreFPGA6"); 84 break; 85 86 default: 87 puts(" CoreUnknown"); 88 } 89 90 putc('\n'); 91 return 0; 92 } 93 94 int board_eth_init(bd_t *bis) 95 { 96 return pci_eth_init(bis); 97 } 98 99 void _machine_restart(void) 100 { 101 void __iomem *reset_base; 102 103 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); 104 __raw_writel(GORESET, reset_base); 105 } 106 107 int board_early_init_f(void) 108 { 109 void *io_base; 110 111 /* choose correct PCI I/O base */ 112 switch (malta_sys_con()) { 113 case SYSCON_GT64120: 114 io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE); 115 break; 116 117 case SYSCON_MSC01: 118 io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); 119 break; 120 121 default: 122 return -1; 123 } 124 125 /* setup FDC37M817 super I/O controller */ 126 malta_superio_init(io_base); 127 128 return 0; 129 } 130 131 struct serial_device *default_serial_console(void) 132 { 133 switch (malta_sys_con()) { 134 case SYSCON_GT64120: 135 return &eserial1_device; 136 137 default: 138 case SYSCON_MSC01: 139 return &eserial2_device; 140 } 141 } 142 143 void pci_init_board(void) 144 { 145 switch (malta_sys_con()) { 146 case SYSCON_GT64120: 147 set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); 148 149 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 150 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 151 0x10000000, 0x10000000, 128 * 1024 * 1024, 152 0x00000000, 0x00000000, 0x20000); 153 break; 154 155 default: 156 case SYSCON_MSC01: 157 set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE)); 158 159 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), 160 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 161 MALTA_MSC01_PCIMEM_MAP, 162 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), 163 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, 164 0x00000000, MALTA_MSC01_PCIIO_SIZE); 165 break; 166 } 167 } 168