1 /* 2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 10 #include <asm/addrspace.h> 11 #include <asm/io.h> 12 #include <asm/malta.h> 13 #include <pci_gt64120.h> 14 15 #include "superio.h" 16 17 phys_size_t initdram(int board_type) 18 { 19 return CONFIG_SYS_MEM_SIZE; 20 } 21 22 int checkboard(void) 23 { 24 puts("Board: MIPS Malta CoreLV (Qemu)\n"); 25 return 0; 26 } 27 28 int board_eth_init(bd_t *bis) 29 { 30 return pci_eth_init(bis); 31 } 32 33 void _machine_restart(void) 34 { 35 void __iomem *reset_base; 36 37 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); 38 __raw_writel(GORESET, reset_base); 39 } 40 41 int board_early_init_f(void) 42 { 43 /* setup FDC37M817 super I/O controller */ 44 malta_superio_init((void *)CKSEG1ADDR(MALTA_IO_PORT_BASE)); 45 46 return 0; 47 } 48 49 void pci_init_board(void) 50 { 51 set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); 52 53 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 54 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 55 0x10000000, 0x10000000, 128 * 1024 * 1024, 56 0x00000000, 0x00000000, 0x20000); 57 } 58