1*7a9d109bSPaul Burton /* 2*7a9d109bSPaul Burton * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 3*7a9d109bSPaul Burton * 4*7a9d109bSPaul Burton * SPDX-License-Identifier: GPL-2.0 5*7a9d109bSPaul Burton */ 6*7a9d109bSPaul Burton 7*7a9d109bSPaul Burton #include <common.h> 8*7a9d109bSPaul Burton #include <netdev.h> 9*7a9d109bSPaul Burton 10*7a9d109bSPaul Burton #include <asm/addrspace.h> 11*7a9d109bSPaul Burton #include <asm/io.h> 12*7a9d109bSPaul Burton #include <asm/malta.h> 13*7a9d109bSPaul Burton #include <pci_gt64120.h> 14*7a9d109bSPaul Burton 15*7a9d109bSPaul Burton phys_size_t initdram(int board_type) 16*7a9d109bSPaul Burton { 17*7a9d109bSPaul Burton return CONFIG_SYS_MEM_SIZE; 18*7a9d109bSPaul Burton } 19*7a9d109bSPaul Burton 20*7a9d109bSPaul Burton int checkboard(void) 21*7a9d109bSPaul Burton { 22*7a9d109bSPaul Burton puts("Board: MIPS Malta CoreLV (Qemu)\n"); 23*7a9d109bSPaul Burton return 0; 24*7a9d109bSPaul Burton } 25*7a9d109bSPaul Burton 26*7a9d109bSPaul Burton int board_eth_init(bd_t *bis) 27*7a9d109bSPaul Burton { 28*7a9d109bSPaul Burton return pci_eth_init(bis); 29*7a9d109bSPaul Burton } 30*7a9d109bSPaul Burton 31*7a9d109bSPaul Burton void _machine_restart(void) 32*7a9d109bSPaul Burton { 33*7a9d109bSPaul Burton void __iomem *reset_base; 34*7a9d109bSPaul Burton 35*7a9d109bSPaul Burton reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); 36*7a9d109bSPaul Burton __raw_writel(GORESET, reset_base); 37*7a9d109bSPaul Burton } 38*7a9d109bSPaul Burton 39*7a9d109bSPaul Burton void pci_init_board(void) 40*7a9d109bSPaul Burton { 41*7a9d109bSPaul Burton set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE)); 42*7a9d109bSPaul Burton 43*7a9d109bSPaul Burton gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), 44*7a9d109bSPaul Burton 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, 45*7a9d109bSPaul Burton 0x10000000, 0x10000000, 128 * 1024 * 1024, 46*7a9d109bSPaul Burton 0x00000000, 0x00000000, 0x20000); 47*7a9d109bSPaul Burton } 48