1 /* 2 * Copyright 2017 General Electric Company 3 * 4 * Based on board/freescale/mx53loco/mx53loco.c: 5 * 6 * Copyright (C) 2011 Freescale Semiconductor, Inc. 7 * Jason Liu <r64343@freescale.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <common.h> 13 #include <asm/io.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/arch/crm_regs.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/iomux-mx53.h> 19 #include <asm/arch/clock.h> 20 #include <linux/errno.h> 21 #include <asm/mach-imx/mxc_i2c.h> 22 #include <asm/mach-imx/mx5_video.h> 23 #include <environment.h> 24 #include <netdev.h> 25 #include <i2c.h> 26 #include <mmc.h> 27 #include <fsl_esdhc.h> 28 #include <asm/gpio.h> 29 #include <power/pmic.h> 30 #include <dialog_pmic.h> 31 #include <fsl_pmic.h> 32 #include <linux/fb.h> 33 #include <ipu_pixfmt.h> 34 #include <watchdog.h> 35 #include "ppd_gpio.h" 36 #include <stdlib.h> 37 #include "../../ge/common/ge_common.h" 38 #include "../../ge/common/vpd_reader.h" 39 40 #define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24) 41 42 DECLARE_GLOBAL_DATA_PTR; 43 44 /* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */ 45 #define VPD_EEPROM_BUS 2 46 47 /* Address of 24C08 EEPROM. */ 48 #define VPD_EEPROM_ADDR 0x50 49 #define VPD_EEPROM_ADDR_LEN 1 50 51 static u32 mx53_dram_size[2]; 52 53 phys_size_t get_effective_memsize(void) 54 { 55 /* 56 * WARNING: We must override get_effective_memsize() function here 57 * to report only the size of the first DRAM bank. This is to make 58 * U-Boot relocator place U-Boot into valid memory, that is, at the 59 * end of the first DRAM bank. If we did not override this function 60 * like so, U-Boot would be placed at the address of the first DRAM 61 * bank + total DRAM size - sizeof(uboot), which in the setup where 62 * each DRAM bank contains 512MiB of DRAM would result in placing 63 * U-Boot into invalid memory area close to the end of the first 64 * DRAM bank. 65 */ 66 return mx53_dram_size[0]; 67 } 68 69 int dram_init(void) 70 { 71 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30); 72 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30); 73 74 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1]; 75 76 return 0; 77 } 78 79 int dram_init_banksize(void) 80 { 81 gd->bd->bi_dram[0].start = PHYS_SDRAM_1; 82 gd->bd->bi_dram[0].size = mx53_dram_size[0]; 83 84 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; 85 gd->bd->bi_dram[1].size = mx53_dram_size[1]; 86 87 return 0; 88 } 89 90 u32 get_board_rev(void) 91 { 92 return get_cpu_rev() & ~(0xF << 8); 93 } 94 95 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 96 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 97 98 #ifdef CONFIG_USB_EHCI_MX5 99 int board_ehci_hcd_init(int port) 100 { 101 /* request VBUS power enable pin, GPIO7_8 */ 102 imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8); 103 gpio_direction_output(IMX_GPIO_NR(7, 8), 1); 104 return 0; 105 } 106 #endif 107 108 static void setup_iomux_fec(void) 109 { 110 static const iomux_v3_cfg_t fec_pads[] = { 111 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS | 112 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | 113 PAD_CTL_ODE), 114 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH), 115 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1, 116 PAD_CTL_HYS | PAD_CTL_PKE), 117 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0, 118 PAD_CTL_HYS | PAD_CTL_PKE), 119 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH), 120 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH), 121 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH), 122 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, 123 PAD_CTL_HYS | PAD_CTL_PKE), 124 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER, 125 PAD_CTL_HYS | PAD_CTL_PKE), 126 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV, 127 PAD_CTL_HYS | PAD_CTL_PKE), 128 }; 129 130 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 131 } 132 133 #ifdef CONFIG_FSL_ESDHC 134 struct fsl_esdhc_cfg esdhc_cfg[2] = { 135 {MMC_SDHC3_BASE_ADDR}, 136 {MMC_SDHC1_BASE_ADDR}, 137 }; 138 139 int board_mmc_getcd(struct mmc *mmc) 140 { 141 return 1; 142 } 143 144 #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ 145 PAD_CTL_PUS_100K_UP) 146 #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ 147 PAD_CTL_DSE_HIGH) 148 149 int board_mmc_init(bd_t *bis) 150 { 151 static const iomux_v3_cfg_t sd1_pads[] = { 152 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD, 153 SD_CMD_PAD_CTRL), 154 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL), 155 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL), 156 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL), 157 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL), 158 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL), 159 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL), 160 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL), 161 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL), 162 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL), 163 MX53_PAD_EIM_DA11__GPIO3_11, 164 }; 165 166 static const iomux_v3_cfg_t sd2_pads[] = { 167 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL), 168 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL), 169 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL), 170 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL), 171 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL), 172 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL), 173 MX53_PAD_EIM_DA13__GPIO3_13, 174 }; 175 176 u32 index; 177 int ret; 178 179 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 180 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 181 182 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) { 183 switch (index) { 184 case 0: 185 imx_iomux_v3_setup_multiple_pads(sd1_pads, 186 ARRAY_SIZE(sd1_pads)); 187 break; 188 case 1: 189 imx_iomux_v3_setup_multiple_pads(sd2_pads, 190 ARRAY_SIZE(sd2_pads)); 191 break; 192 default: 193 printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n", 194 CONFIG_SYS_FSL_ESDHC_NUM); 195 return -EINVAL; 196 } 197 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]); 198 if (ret) 199 return ret; 200 } 201 202 return 0; 203 } 204 #endif 205 206 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 207 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE) 208 209 static void setup_iomux_i2c(void) 210 { 211 static const iomux_v3_cfg_t i2c1_pads[] = { 212 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL), 213 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL), 214 }; 215 216 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); 217 } 218 219 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) 220 221 static struct i2c_pads_info i2c_pad_info1 = { 222 .scl = { 223 .i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD, 224 .gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD, 225 .gp = IMX_GPIO_NR(3, 28) 226 }, 227 .sda = { 228 .i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD, 229 .gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD, 230 .gp = IMX_GPIO_NR(3, 21) 231 } 232 }; 233 234 static int clock_1GHz(void) 235 { 236 int ret; 237 u32 ref_clk = MXC_HCLK; 238 /* 239 * After increasing voltage to 1.25V, we can switch 240 * CPU clock to 1GHz and DDR to 400MHz safely 241 */ 242 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); 243 if (ret) { 244 printf("CPU: Switch CPU clock to 1GHZ failed\n"); 245 return -1; 246 } 247 248 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); 249 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); 250 if (ret) { 251 printf("CPU: Switch DDR clock to 400MHz failed\n"); 252 return -1; 253 } 254 255 return 0; 256 } 257 258 void ppd_gpio_init(void) 259 { 260 int i; 261 262 imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads)); 263 for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i) 264 gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value); 265 } 266 267 int board_early_init_f(void) 268 { 269 setup_iomux_fec(); 270 setup_iomux_lcd(); 271 ppd_gpio_init(); 272 273 return 0; 274 } 275 276 /* 277 * Do not overwrite the console 278 * Use always serial for U-Boot console 279 */ 280 int overwrite_console(void) 281 { 282 return 1; 283 } 284 285 #define VPD_TYPE_INVALID 0x00 286 #define VPD_BLOCK_NETWORK 0x20 287 #define VPD_BLOCK_HWID 0x44 288 #define VPD_PRODUCT_PPD 4 289 #define VPD_HAS_MAC1 0x1 290 #define VPD_MAC_ADDRESS_LENGTH 6 291 292 struct vpd_cache { 293 u8 product_id; 294 u8 has; 295 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH]; 296 }; 297 298 /* 299 * Extracts MAC and product information from the VPD. 300 */ 301 static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size, 302 u8 const *data) 303 { 304 struct vpd_cache *vpd = (struct vpd_cache *)userdata; 305 306 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID && 307 size >= 1) { 308 vpd->product_id = data[0]; 309 310 } else if (id == VPD_BLOCK_NETWORK && version == 1 && 311 type != VPD_TYPE_INVALID) { 312 if (size >= 6) { 313 vpd->has |= VPD_HAS_MAC1; 314 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH); 315 } 316 } 317 318 return 0; 319 } 320 321 static void process_vpd(struct vpd_cache *vpd) 322 { 323 int fec_index = -1; 324 325 if (vpd->product_id == VPD_PRODUCT_PPD) 326 fec_index = 0; 327 328 if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1)) 329 eth_env_set_enetaddr("ethaddr", vpd->mac1); 330 } 331 332 static int read_vpd(uint eeprom_bus) 333 { 334 struct vpd_cache vpd; 335 int res; 336 int size = 1024; 337 u8 *data; 338 unsigned int current_i2c_bus = i2c_get_bus_num(); 339 340 res = i2c_set_bus_num(eeprom_bus); 341 if (res < 0) 342 return res; 343 344 data = malloc(size); 345 if (!data) 346 return -ENOMEM; 347 348 res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size); 349 if (res == 0) { 350 memset(&vpd, 0, sizeof(vpd)); 351 vpd_reader(size, data, &vpd, vpd_callback); 352 process_vpd(&vpd); 353 } 354 355 free(data); 356 357 i2c_set_bus_num(current_i2c_bus); 358 return res; 359 } 360 361 int board_init(void) 362 { 363 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 364 365 mxc_set_sata_internal_clock(); 366 setup_iomux_i2c(); 367 368 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 369 370 return 0; 371 } 372 373 int misc_init_r(void) 374 { 375 const char *cause; 376 377 /* We care about WDOG only, treating everything else as 378 * a power-on-reset. 379 */ 380 if (get_imx_reset_cause() & 0x0010) 381 cause = "WDOG"; 382 else 383 cause = "POR"; 384 385 env_set("bootcause", cause); 386 387 return 0; 388 } 389 390 int board_late_init(void) 391 { 392 int res; 393 394 read_vpd(VPD_EEPROM_BUS); 395 396 res = clock_1GHz(); 397 if (res != 0) 398 return res; 399 400 print_cpuinfo(); 401 hw_watchdog_init(); 402 403 check_time(); 404 405 return 0; 406 } 407 408 int checkboard(void) 409 { 410 puts("Board: GE PPD\n"); 411 412 return 0; 413 } 414