xref: /openbmc/u-boot/board/gdsys/p1022/ddr.c (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2b9944a77SDirk Eibach /*
3b9944a77SDirk Eibach  * Copyright 2010 Freescale Semiconductor, Inc.
4b9944a77SDirk Eibach  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5b9944a77SDirk Eibach  *          Timur Tabi <timur@freescale.com>
6b9944a77SDirk Eibach  */
7b9944a77SDirk Eibach 
8b9944a77SDirk Eibach #include <common.h>
9b9944a77SDirk Eibach #include <i2c.h>
10b9944a77SDirk Eibach 
115614e71bSYork Sun #include <fsl_ddr_sdram.h>
125614e71bSYork Sun #include <fsl_ddr_dimm_params.h>
13b9944a77SDirk Eibach 
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)14b9944a77SDirk Eibach void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
15b9944a77SDirk Eibach 			   unsigned int ctrl_num)
16b9944a77SDirk Eibach {
17b9944a77SDirk Eibach 	unsigned int i;
18b9944a77SDirk Eibach 
19b9944a77SDirk Eibach 	if (ctrl_num) {
20b9944a77SDirk Eibach 		printf("Wrong parameter for controller number %d", ctrl_num);
21b9944a77SDirk Eibach 		return;
22b9944a77SDirk Eibach 	}
23b9944a77SDirk Eibach 	if (!pdimm->n_ranks)
24b9944a77SDirk Eibach 		return;
25b9944a77SDirk Eibach 
26b9944a77SDirk Eibach 	/* set odt_rd_cfg and odt_wr_cfg. */
27b9944a77SDirk Eibach 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
28b9944a77SDirk Eibach 		popts->cs_local_opts[i].odt_rd_cfg = 0;
29b9944a77SDirk Eibach 		popts->cs_local_opts[i].odt_wr_cfg = 1;
30b9944a77SDirk Eibach 	}
31b9944a77SDirk Eibach 
32b9944a77SDirk Eibach 	popts->clk_adjust = 5;
33b9944a77SDirk Eibach 	popts->cpo_override = 0x1f;
34b9944a77SDirk Eibach 	popts->write_data_delay = 2;
35b9944a77SDirk Eibach 	popts->half_strength_driver_enable = 1;
36b9944a77SDirk Eibach 
37b9944a77SDirk Eibach 	/* Per AN4039, enable ZQ calibration. */
38b9944a77SDirk Eibach 	popts->zq_en = 1;
39b9944a77SDirk Eibach }
40b9944a77SDirk Eibach 
41b9944a77SDirk Eibach #ifdef CONFIG_SPD_EEPROM
42b9944a77SDirk Eibach /*
43b9944a77SDirk Eibach  * we only have a "fake" SPD-EEPROM here, which has 16 bit addresses
44b9944a77SDirk Eibach  */
get_spd(generic_spd_eeprom_t * spd,u8 i2c_address)45b9944a77SDirk Eibach void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
46b9944a77SDirk Eibach {
47b9944a77SDirk Eibach 	int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd,
48b9944a77SDirk Eibach 				sizeof(generic_spd_eeprom_t));
49b9944a77SDirk Eibach 
50b9944a77SDirk Eibach 	if (ret) {
51b9944a77SDirk Eibach 		if (i2c_address ==
52b9944a77SDirk Eibach #ifdef SPD_EEPROM_ADDRESS
53b9944a77SDirk Eibach 				SPD_EEPROM_ADDRESS
54b9944a77SDirk Eibach #elif defined(SPD_EEPROM_ADDRESS1)
55b9944a77SDirk Eibach 				SPD_EEPROM_ADDRESS1
56b9944a77SDirk Eibach #endif
57b9944a77SDirk Eibach 				) {
58b9944a77SDirk Eibach 			printf("DDR: failed to read SPD from address %u\n",
59b9944a77SDirk Eibach 			       i2c_address);
60b9944a77SDirk Eibach 		} else {
61b9944a77SDirk Eibach 			debug("DDR: failed to read SPD from address %u\n",
62b9944a77SDirk Eibach 			      i2c_address);
63b9944a77SDirk Eibach 		}
64b9944a77SDirk Eibach 		memset(spd, 0, sizeof(generic_spd_eeprom_t));
65b9944a77SDirk Eibach 	}
66b9944a77SDirk Eibach }
67b9944a77SDirk Eibach #endif
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