18d67c368SShengzhou Liu /* 28d67c368SShengzhou Liu * Copyright 2014 Freescale Semiconductor, Inc. 38d67c368SShengzhou Liu * 48d67c368SShengzhou Liu * Shengzhou Liu <Shengzhou.Liu@freescale.com> 58d67c368SShengzhou Liu * 68d67c368SShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 78d67c368SShengzhou Liu */ 88d67c368SShengzhou Liu 98d67c368SShengzhou Liu #include <common.h> 108d67c368SShengzhou Liu #include <command.h> 118d67c368SShengzhou Liu #include <netdev.h> 128d67c368SShengzhou Liu #include <asm/mmu.h> 138d67c368SShengzhou Liu #include <asm/processor.h> 148d67c368SShengzhou Liu #include <asm/immap_85xx.h> 158d67c368SShengzhou Liu #include <asm/fsl_law.h> 168d67c368SShengzhou Liu #include <asm/fsl_serdes.h> 178d67c368SShengzhou Liu #include <asm/fsl_portals.h> 188d67c368SShengzhou Liu #include <asm/fsl_liodn.h> 198d67c368SShengzhou Liu #include <malloc.h> 208d67c368SShengzhou Liu #include <fm_eth.h> 218d67c368SShengzhou Liu #include <fsl_mdio.h> 228d67c368SShengzhou Liu #include <miiphy.h> 238d67c368SShengzhou Liu #include <phy.h> 24*8225b2fdSShaohui Xie #include <fsl_dtsec.h> 258d67c368SShengzhou Liu #include <asm/fsl_serdes.h> 268d67c368SShengzhou Liu 278d67c368SShengzhou Liu int board_eth_init(bd_t *bis) 288d67c368SShengzhou Liu { 298d67c368SShengzhou Liu #if defined(CONFIG_FMAN_ENET) 308d67c368SShengzhou Liu int i, interface; 318d67c368SShengzhou Liu struct memac_mdio_info dtsec_mdio_info; 328d67c368SShengzhou Liu struct memac_mdio_info tgec_mdio_info; 338d67c368SShengzhou Liu struct mii_dev *dev; 348d67c368SShengzhou Liu ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 358d67c368SShengzhou Liu u32 srds_s1; 368d67c368SShengzhou Liu 378d67c368SShengzhou Liu srds_s1 = in_be32(&gur->rcwsr[4]) & 388d67c368SShengzhou Liu FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 398d67c368SShengzhou Liu srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 408d67c368SShengzhou Liu 418d67c368SShengzhou Liu dtsec_mdio_info.regs = 428d67c368SShengzhou Liu (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; 438d67c368SShengzhou Liu 448d67c368SShengzhou Liu dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 458d67c368SShengzhou Liu 468d67c368SShengzhou Liu /* Register the 1G MDIO bus */ 478d67c368SShengzhou Liu fm_memac_mdio_init(bis, &dtsec_mdio_info); 488d67c368SShengzhou Liu 498d67c368SShengzhou Liu tgec_mdio_info.regs = 508d67c368SShengzhou Liu (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 518d67c368SShengzhou Liu tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 528d67c368SShengzhou Liu 538d67c368SShengzhou Liu /* Register the 10G MDIO bus */ 548d67c368SShengzhou Liu fm_memac_mdio_init(bis, &tgec_mdio_info); 558d67c368SShengzhou Liu 568d67c368SShengzhou Liu /* Set the two on-board RGMII PHY address */ 578d67c368SShengzhou Liu fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); 588d67c368SShengzhou Liu fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); 598d67c368SShengzhou Liu 608d67c368SShengzhou Liu switch (srds_s1) { 618d67c368SShengzhou Liu case 0x66: 628d67c368SShengzhou Liu case 0x6b: 638d67c368SShengzhou Liu fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1); 648d67c368SShengzhou Liu fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2); 658d67c368SShengzhou Liu fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR); 668d67c368SShengzhou Liu fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR); 678d67c368SShengzhou Liu break; 688d67c368SShengzhou Liu default: 698d67c368SShengzhou Liu printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n", 708d67c368SShengzhou Liu srds_s1); 718d67c368SShengzhou Liu break; 728d67c368SShengzhou Liu } 738d67c368SShengzhou Liu 748d67c368SShengzhou Liu for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 758d67c368SShengzhou Liu interface = fm_info_get_enet_if(i); 768d67c368SShengzhou Liu switch (interface) { 778d67c368SShengzhou Liu case PHY_INTERFACE_MODE_RGMII: 788d67c368SShengzhou Liu dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); 798d67c368SShengzhou Liu fm_info_set_mdio(i, dev); 808d67c368SShengzhou Liu break; 818d67c368SShengzhou Liu default: 828d67c368SShengzhou Liu break; 838d67c368SShengzhou Liu } 848d67c368SShengzhou Liu } 858d67c368SShengzhou Liu 868d67c368SShengzhou Liu for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 878d67c368SShengzhou Liu switch (fm_info_get_enet_if(i)) { 888d67c368SShengzhou Liu case PHY_INTERFACE_MODE_XGMII: 898d67c368SShengzhou Liu dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); 908d67c368SShengzhou Liu fm_info_set_mdio(i, dev); 918d67c368SShengzhou Liu break; 928d67c368SShengzhou Liu default: 938d67c368SShengzhou Liu break; 948d67c368SShengzhou Liu } 958d67c368SShengzhou Liu } 968d67c368SShengzhou Liu 978d67c368SShengzhou Liu cpu_eth_init(bis); 988d67c368SShengzhou Liu #endif /* CONFIG_FMAN_ENET */ 998d67c368SShengzhou Liu 1008d67c368SShengzhou Liu return pci_eth_init(bis); 1018d67c368SShengzhou Liu } 1028d67c368SShengzhou Liu 1038d67c368SShengzhou Liu void fdt_fixup_board_enet(void *fdt) 1048d67c368SShengzhou Liu { 1058d67c368SShengzhou Liu return; 1068d67c368SShengzhou Liu } 107