1b19e288fSShengzhou Liu /* Copyright 2013 Freescale Semiconductor, Inc. 2b19e288fSShengzhou Liu * 3b19e288fSShengzhou Liu * SPDX-License-Identifier: GPL-2.0+ 4b19e288fSShengzhou Liu */ 5b19e288fSShengzhou Liu 6b19e288fSShengzhou Liu #include <common.h> 724b852a7SSimon Glass #include <console.h> 8b19e288fSShengzhou Liu #include <malloc.h> 9b19e288fSShengzhou Liu #include <ns16550.h> 10b19e288fSShengzhou Liu #include <nand.h> 11b19e288fSShengzhou Liu #include <i2c.h> 12b19e288fSShengzhou Liu #include <mmc.h> 13b19e288fSShengzhou Liu #include <fsl_esdhc.h> 14b19e288fSShengzhou Liu #include <spi_flash.h> 15b19e288fSShengzhou Liu #include "../common/qixis.h" 16b19e288fSShengzhou Liu #include "t208xqds_qixis.h" 17ea022a37SSimon Glass #include "../common/spl.h" 18b19e288fSShengzhou Liu 19b19e288fSShengzhou Liu DECLARE_GLOBAL_DATA_PTR; 20b19e288fSShengzhou Liu 21b19e288fSShengzhou Liu phys_size_t get_effective_memsize(void) 22b19e288fSShengzhou Liu { 23b19e288fSShengzhou Liu return CONFIG_SYS_L3_SIZE; 24b19e288fSShengzhou Liu } 25b19e288fSShengzhou Liu 26b19e288fSShengzhou Liu unsigned long get_board_sys_clk(void) 27b19e288fSShengzhou Liu { 28b19e288fSShengzhou Liu u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 29b19e288fSShengzhou Liu 30b19e288fSShengzhou Liu switch (sysclk_conf & 0x0F) { 31b19e288fSShengzhou Liu case QIXIS_SYSCLK_83: 32b19e288fSShengzhou Liu return 83333333; 33b19e288fSShengzhou Liu case QIXIS_SYSCLK_100: 34b19e288fSShengzhou Liu return 100000000; 35b19e288fSShengzhou Liu case QIXIS_SYSCLK_125: 36b19e288fSShengzhou Liu return 125000000; 37b19e288fSShengzhou Liu case QIXIS_SYSCLK_133: 38b19e288fSShengzhou Liu return 133333333; 39b19e288fSShengzhou Liu case QIXIS_SYSCLK_150: 40b19e288fSShengzhou Liu return 150000000; 41b19e288fSShengzhou Liu case QIXIS_SYSCLK_160: 42b19e288fSShengzhou Liu return 160000000; 43b19e288fSShengzhou Liu case QIXIS_SYSCLK_166: 44b19e288fSShengzhou Liu return 166666666; 45b19e288fSShengzhou Liu } 46b19e288fSShengzhou Liu return 66666666; 47b19e288fSShengzhou Liu } 48b19e288fSShengzhou Liu 49b19e288fSShengzhou Liu unsigned long get_board_ddr_clk(void) 50b19e288fSShengzhou Liu { 51b19e288fSShengzhou Liu u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 52b19e288fSShengzhou Liu 53b19e288fSShengzhou Liu switch ((ddrclk_conf & 0x30) >> 4) { 54b19e288fSShengzhou Liu case QIXIS_DDRCLK_100: 55b19e288fSShengzhou Liu return 100000000; 56b19e288fSShengzhou Liu case QIXIS_DDRCLK_125: 57b19e288fSShengzhou Liu return 125000000; 58b19e288fSShengzhou Liu case QIXIS_DDRCLK_133: 59b19e288fSShengzhou Liu return 133333333; 60b19e288fSShengzhou Liu } 61b19e288fSShengzhou Liu return 66666666; 62b19e288fSShengzhou Liu } 63b19e288fSShengzhou Liu 64b19e288fSShengzhou Liu void board_init_f(ulong bootflag) 65b19e288fSShengzhou Liu { 66b19e288fSShengzhou Liu u32 plat_ratio, sys_clk, ccb_clk; 67b19e288fSShengzhou Liu ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 68b19e288fSShengzhou Liu 69b19e288fSShengzhou Liu /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 70b19e288fSShengzhou Liu memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 71b19e288fSShengzhou Liu 72b19e288fSShengzhou Liu /* Update GD pointer */ 73b19e288fSShengzhou Liu gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 74b19e288fSShengzhou Liu 75b19e288fSShengzhou Liu console_init_f(); 76b19e288fSShengzhou Liu 77b19e288fSShengzhou Liu /* initialize selected port with appropriate baud rate */ 78b19e288fSShengzhou Liu sys_clk = get_board_sys_clk(); 79b19e288fSShengzhou Liu plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 80b19e288fSShengzhou Liu ccb_clk = sys_clk * plat_ratio / 2; 81b19e288fSShengzhou Liu 82b19e288fSShengzhou Liu NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 83b19e288fSShengzhou Liu ccb_clk / 16 / CONFIG_BAUDRATE); 84b19e288fSShengzhou Liu 85b19e288fSShengzhou Liu #if defined(CONFIG_SPL_MMC_BOOT) 86b19e288fSShengzhou Liu puts("\nSD boot...\n"); 87b19e288fSShengzhou Liu #elif defined(CONFIG_SPL_SPI_BOOT) 88b19e288fSShengzhou Liu puts("\nSPI boot...\n"); 89b19e288fSShengzhou Liu #elif defined(CONFIG_SPL_NAND_BOOT) 90b19e288fSShengzhou Liu puts("\nNAND boot...\n"); 91b19e288fSShengzhou Liu #endif 92b19e288fSShengzhou Liu 93b19e288fSShengzhou Liu relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 94b19e288fSShengzhou Liu } 95b19e288fSShengzhou Liu 96b19e288fSShengzhou Liu void board_init_r(gd_t *gd, ulong dest_addr) 97b19e288fSShengzhou Liu { 98b19e288fSShengzhou Liu bd_t *bd; 99b19e288fSShengzhou Liu 100b19e288fSShengzhou Liu bd = (bd_t *)(gd + sizeof(gd_t)); 101b19e288fSShengzhou Liu memset(bd, 0, sizeof(bd_t)); 102b19e288fSShengzhou Liu gd->bd = bd; 103b19e288fSShengzhou Liu bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 104b19e288fSShengzhou Liu bd->bi_memsize = CONFIG_SYS_L3_SIZE; 105b19e288fSShengzhou Liu 106*cbcbf71bSSimon Glass arch_cpu_init(); 107b19e288fSShengzhou Liu get_clocks(); 108b19e288fSShengzhou Liu mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 109b19e288fSShengzhou Liu CONFIG_SPL_RELOC_MALLOC_SIZE); 110ed4708aaSSumit Garg gd->flags |= GD_FLG_FULL_MALLOC_INIT; 111b19e288fSShengzhou Liu 112b19e288fSShengzhou Liu #ifdef CONFIG_SPL_NAND_BOOT 113b19e288fSShengzhou Liu nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 114b19e288fSShengzhou Liu (uchar *)CONFIG_ENV_ADDR); 115b19e288fSShengzhou Liu #endif 116b19e288fSShengzhou Liu #ifdef CONFIG_SPL_MMC_BOOT 117b19e288fSShengzhou Liu mmc_initialize(bd); 118b19e288fSShengzhou Liu mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 119b19e288fSShengzhou Liu (uchar *)CONFIG_ENV_ADDR); 120b19e288fSShengzhou Liu #endif 121b19e288fSShengzhou Liu #ifdef CONFIG_SPL_SPI_BOOT 122ea022a37SSimon Glass fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 123b19e288fSShengzhou Liu (uchar *)CONFIG_ENV_ADDR); 124b19e288fSShengzhou Liu #endif 125b19e288fSShengzhou Liu 126b19e288fSShengzhou Liu gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 127b19e288fSShengzhou Liu gd->env_valid = 1; 128b19e288fSShengzhou Liu 129b19e288fSShengzhou Liu i2c_init_all(); 130b19e288fSShengzhou Liu 131b19e288fSShengzhou Liu gd->ram_size = initdram(0); 132b19e288fSShengzhou Liu 133b19e288fSShengzhou Liu #ifdef CONFIG_SPL_MMC_BOOT 134b19e288fSShengzhou Liu mmc_boot(); 135b19e288fSShengzhou Liu #elif defined(CONFIG_SPL_SPI_BOOT) 136ea022a37SSimon Glass fsl_spi_boot(); 137b19e288fSShengzhou Liu #elif defined(CONFIG_SPL_NAND_BOOT) 138b19e288fSShengzhou Liu nand_boot(); 139b19e288fSShengzhou Liu #endif 140b19e288fSShengzhou Liu } 141